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SUBSTRATE NOISE

The significant problems we face cannot be solved

by the same level of thinking that created them”

(Albert Einstein)

  1. Mendonca dos Santos P., Mendes Luis, Vaz Joao Caldinhas: Substrate noise isolation improvement in a single-well standard CMOS process. Integration - the VLSI Journal, Vol. 52, 2016, pp. 122 – 128. DOI 10.1016/j.vlsi.2015.09.006

  2. Gaynor B.D., Hassoun S.: Simulation Methodology and Evaluation of Through Silicon Via (TSV)-FinFET Noise Coupling in 3-D Integrated Circuits. IEEE Trans on VLSI, Vol. 23, no. 8, 2015, pp. 1499 – 1507. DOI 10.1109/TVLSI.2014.2341834

  3. Stefanucci C., Buccella P., Kayal M., Sallese J.-M.: Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs. IEEE Trans on ED, Vol. 62, no. 4, 2015, pp. 1215 – 1222. DOI 10.1109/TED.2015.2397394

  4. Stefanucci C., Buccella P., Kayal M., Sallese J.-M.: Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs. Solid-State Electronics, Vol. 105, 2015, pp. 21 – 29. DOI 10.1016/j.sse.2014.11.016

  5. Zhao Yingbo, Dong Gang, Yang Yintang, Zheng Junping: Analysis and evaluation of coupling between adjacent TSVs with considering the discharging path. IEICE Electronics Express, Vol. 12, no. 5, 2015, pp. 20150089. DOI 10.1587/elex.12.20150089

  6. Yang Ziqiang, Luo Bangyu, Dong Jun, Yang Tao, Jin Haiyan: Low phase noise oscillator based on quarter mode substrate integrated waveguide technique. IEICE Electronics Express, Vol. 12, no. 6, 2015, Article # 20150046. DOI 10.1587/elex.12.20150046

  7. Li Ning, Okada Kenichi, Inoue Takeshi, Hirano Takuichi, et al.: High-Q Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits. IEEE Trans on ED, Vol. 62, no. 4, 2015, pp. 1269 – 1275. DOI 10.1109/TED.2015.2403873

  8. Eriksson K., Gunnarsson S.E., Nilsson P.-A., Zirath H.: Suppression of Parasitic Substrate Modes in Multilayer Integrated Circuits. IEEE Trans on EMC, Vol. 57, no. 3, 2015, pp. 591 – 594. DOI 10.1109/TEMC.2015.2393359

  9. Chahadih A., Cresson P.Y., Mismer C., Lasri T.: V-Band Via-Less GCPW-to-Microstrip Transition Designed on PET Flexible Substrate Using Inkjet Printing Technology. IEEE Microwave & Wireless Comp. Lett., Vol. 25, no. 7, 2015, pp. 436 – 438. DOI 10.1109/LMWC.2015.2427576

  10. Noulis T., Baumgartner P.: Substrate crosstalk analysis flow for submicron CMOS system-on-chip. Electronics Lett., Vol. 51, no. 12, 2015, pp. 953 – 954. DOI 10.1049/el.2015.0563

  11. Noulis T., Lourandakis E., Stefanou S., Merakos P.: CMOS 65 nm 'on chip' broadband real time substrate noise measurement. Electronics Lett., Vol. 51, no. 21, 2015, pp. 1710 – U107. DOI 10.1049/el.2015.2099

  12. Yu Panpan, Chen Bo, Gao Jianjun: Microwave noise modeling for MOSFETs. Int. J. of Numerical Modelling - Electronic Networks Devices & Fields, Vol. 28 no. 6, 2015, Special Issue: SI, pp. 639 – 648. DOI 10.1002/jnm.2061

  13. Doria R.T., Sodre de Souza M.A., Martino J.A., Simoen E., Claeys C., Pavanello M. A.: In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs. Microelectronic Engineering, Vol. 147, 2015, pp. 92 – 95. DOI 10.1016/j.mee.2015.04.056

  14. Bao Shiyong, Du Mingliang, Zhang Ming, et al.: Facile fabrication of polyaniline nanotubes/gold hybrid nanostructures as substrate materials for biosensors. Chemical Engineering J., Vol. 258, 2014, pp. 281 – 289. DOI 10.1016/j.cej.2014.07.078

  15. Peng Y., Song T., Petranovic D., Lim Sung Kyu: Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling. IEEE Trans on CAD of Integrated Circuits and Systems, Vol. 33, no. 12, 2014, pp. 1900 – 1913. DOI 10.1109/TCAD.2014.2359578

  16. Bermond C., Brocard M., Lacrevaz T., et al.: RF characterization of the substrate coupling noise between TSV and active devices in 3D integrated circuits. Microelectronic Engineering, Vol. 130, 2014, pp. 74 – 81. DOI 10.1016/j.mee.2014.09.025

  17. Chun-Ho Jeong, Jong-Phil Hong: Analysis of substrate shielding methods for sub-THz on-chip inductors. Electronics Lett., Vol. 50, no. 22, 2014, pp. 1613 – 1615. DOI 10.1049/el.2014.2992

  18. Qimeng Jiang, Zhikai Tang, Chunhua Zhou, Shu Yang, Chen K.J.: Substrate-Coupled Cross-Talk Effects on an AlGaN/GaN-on-Si Smart Power IC Platform. IEEE Trans on ED, Vol. 61, no. 11, 2014, pp. 3808 – 3813. DOI 10.1109/TED.2014.2355834

  19. Bo Zhang, Wentong Zhang, Zehong Li, Ming Qiao, Zhaoji Li: Equivalent Substrate Model for Lateral Super Junction Device. IEEE Trans on ED, Vol. 61, no. 2, 2014, pp. 525 – 532. DOI 10.1109/TED.2013.2295091

  20. Veerappan C., Charbon E.: A Substrate Isolated CMOS SPAD Enabling Wide Spectral Response and Low Electrical Crosstalk. IEEE Journal of Selected Topics in Quantum Electronics, Vol. 20, no. 6, 2014, pp. 299 – 305. DOI 10.1109/JSTQE.2014.2318436

  21. B. Gaynor, S. Hassoun: Parasitic Back-Gate Effect in 3-D Fully Depleted Silicon on Insulator Integrated Circuits. IEEE Trans on Components, Packaging & Manufacturing Technology, Vol. 4, no. 1, 2014, pp. 100 – 108. DOI 10.1109/TCPMT.2013.2272401

  22. Putranto Dedy Septono Catur, Priambodo Purnomo Sidi, Hartanto Djoko, Du Wei, Satoh Hiroaki, Ono Atsushi, Inokawa Hiroshi: Effects of substrate voltage on noise characteristics and hole lifetime in SOI metal-oxide-semiconductor field-effect transistor photon detector. Optics Express, Vol. 22, no. 18, 2014, pp. 22072 – 22079. DOI 10.1364/OE.22.022072

  23. Ong Shih Ni, Yeo Kiat Seng, Chew Kok Wai Johnny, Chan Lye Hock Kelvin: Substrate-Induced Noise Model and Parameter Extraction for High-Frequency Noise Modeling of Sub-Micron MOSFETs. IEEE Trans on MTT, Vol. 62, no. 9, 2014, Special Issue: SI pp. 1973 – 1985. DOI 10.1109/TMTT.2014.2340375

  24. Werquin S., Vermeulen D., Bienstman P.: Implementation of Surface Gratings for Reduced Coupling Noise in Silicon-on-Insulator Circuits. IEEE Photonics Technology Lett., Vol. 26, no. 16, 2014, pp. 1589 – 1592. DOI 10.1109/LPT.2014.2326735

  25. Preibisch J.B., Duan Xiaomin, Schuster C.: An Efficient Analysis of Power/Ground Planes With Inhomogeneous Substrates Using the Contour Integral Method. IEEE Trans on EMC, Vol. 56, no. 4, 2014, pp. 980 – 989. DOI 10.1109/TEMC.2013.2292095

  26. Azuma Naoya, Shimazaki Shunsuke, Miura Noriyuki, et al.: Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator. IEICE Trans on Electronics, Vol. E97C, no. 6, 2014, pp. 546 – 556. DOI 10.1587/transele.E97.C.546

  27. Wang Hailang, Asgari Mohammad H., Salman Emre: Compact model to efficiently characterize TSV-to-transistor noise coupling in 3D ICs. Integration - the VLSI Journal, Vol. 47, no. 3, 2014, SI, pp. 296 – 306. DOI 10.1016/j.vlsi.2013.10.006

  28. Shimazaki Shunsuke, Taga Shota, Makita Tetsuya, Azuma Naoya, Miura Noriyuki, Nagata Makoto: Emulation of high-frequency substrate noise generation in CMOS digital circuits. Japanese Journal of Applied Physics, Vol. 53, no. 4, 2014, SI, Article # 04EE06. DOI 10.7567/JJAP.53.04EE06

  29. Ben Ali K., Neve Cesar Roda, Gharsallah A., et al.: RF Performance of SOI CMOS Technology on Commercial 200-mm Enhanced Signal Integrity High Resistivity SOI Substrate. IEEE Trans on ED, Vol. 61, no. 3, 2014, pp. 722 – 728. DOI 10.1109/TED.2014.2302685

  30. Kanamoto Toshiki, Inaba Hisato, Chiba Toshiharu, Ogasahara Yasuhiro: Resistivity-based modeling of substrate non-uniformity for low-resistivity substrate. IEICE Electronics Express, Vol. 11, no. 3, 2014, Article # 20130813. DOI 10.1587/elex.11.20130813

  31. Jia-Yi Wu, Mu-Shui Zhang, Hong-Zhou Tan, Yong-Xin Guo: Substrate noise coupling isolation using P+ contact array and grid ground plane in RF/mixed-signal 3D TSV ICs. IEEE 23rd Conf on Electrical Performance of Electronic Packaging & Systems (EPEPS), 2014, pp. 183 – 186. DOI 10.1109/EPEPS.2014.7103629

  32. Araga Yuuki, Nagata Makoto, Van der Plas G., et al.: Measurements and Analysis of Substrate Noise Coupling in TSV-Based 3-D Integrated Circuits. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 4, no. 6, 2014, pp. 1026 – 1037. DOI 10.1109/TCPMT.2014.2316150

  33. Gontrand C., Sun F., Ricardo Cardenas-Valdez J., et al. : 3D substrate modeling, from a first order electrical analysis, towards some possible signal fluctuations consideration, for radio frequency circuits. Microelectronics J., Vol. 45, no. 8, 2014, pp. 1061 – 1068. DOI 10.1016/j.mejo.2014.04.037

  34. Lin Leo J.-H., Chiou Y.-P.: 3-D Transient Analysis of TSV-Induced Substrate Noise: Improved Noise Reduction in 3-D-ICs With Incorporation of Guarding Structures. IEEE ED Lett., Vol. 35, no. 6, 2014, pp. 660 – 662. DOI 10.1109/LED.2014.2318301

  35. Singh P.K., Sharma S.: Substrate Coupling of RF CMOS on Lightly Doped Substrate for Nanoscale Mixed-Signal Design. J. of Computational and Theoretical Nanoscience, Vol. 11, no. 4, 2014, pp. 1184 – 1188. DOI 10.1166/jctn.2014.3480

  36. Wong Sai Wai, Wang Kai, Chen Zhi-Ning, Chu Qing-Xin: Electric Coupling Structure of Substrate Integrated Waveguide (SIW) for the Application of 140-GHz Bandpass Filter on LTCC. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 4, no. 2, 2014, pp. 316 – 322. DOI 10.1109/TCPMT.2013.2285388

  37. Bontzios Y.I., Dimopoulos M.G., Dimitriadis A.I., Hatzopoulos A.A: Exact closed-form expressions for substrate resistance and capacitance extraction in nanoscale VLSI. Microelectronics J., Vol. 44, no. 12, 2013, pp. 1077 – 1083. DOI 10.1016/j.mejo.2012.12.002

  38. Manikandan R.R., Amrutur B.: Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance. IEEE Trans on CAS II : Express Briefs, Vol. 60, no. 12, 2013, pp. 852 – 856. DOI 10.1109/TCSII.2013.2281942

  39. Gu X., Silberman J.A., Young A.M., et al.: Characterization of TSV-Induced Loss and Substrate Noise Coupling in Advanced Three-Dimensional CMOS SOI Technology. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 3, no. 11, 2013, pp. 1917 – 1925. DOI 10.1109/TCPMT.2013.2264755

  40. Brocard M., Bermond C., Lacrevaz T., et al. : RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuits. IEEE Int. 3D Systems Integration Conf. (3DIC), 2013, pp. 1 – 8. DOI 10.1109/3DIC.2013.6702331

  41. Aboul-Yazeed Mohamed Saleh, El-Rouby Alaa, Hussien Ahmad: Lumped Elements Model for Substrate Noise Coupling. Saudi Int. Electronics, Comm. & Photonics Conf. (SIECPC), 2013.

  42. Ben Salah M., Pasquet D., Voiron F., Descamps P., Lefebvre J.-L., Lesenechal D.: Reducing Substrate Noise Coupling in a 3D-PICS Integrated Passive Device by localized P plus Guard Rings. IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Syst. (SiRF), 2013, pp. 204 – 206.

  43. Ogasahara Y., Hashimoto M., Kanamoto T., Onoye T.: Supply Noise Suppression by Triple-Well Structure. IEEE Trans on VLSI, Vol. 21, no. 4, 2013, pp.781 – 785. DOI 10.1109/TVLSI.2012.2192458

  44. Youngae Han, Jinsong Zhao: Accurate Substrate Analysis Based on a Novel Finite Difference Method via Synchronization Method on Layered and Adaptive Meshing. IEEE Trans on CAD of Integrated Circuits and Systems, Vol. 32, no. 10, 2013, pp.1520 – 1532. DOI 10.1109/TCAD.2013.2261437

  45. Khan N.H., Alam S.M., Hassoun S.: GND Plugs: A Superior Technology to Mitigate TSV-Induced Substrate Noise. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 3, no. 5, 2013, pp. 849 – 857. DOI 10.1109/TCPMT.2013.2241178

  46. Azuma Naoya, Nagata Makoto: Equivalent Circuit Representation of Silicon Substrate Coupling of Passive and Active RF Components. IEICE Trans on Electronics, Vol. E96C, no. 6, 2013, pp. 875 – 883. DOI 10.1587/transele.E96.C.875

  47. Osmany S.A., Herzel F., Scheytt J.C.: Analysis and minimization of substrate spurs in fractional-N frequency synthesizers. Analog Integrated Circuits & Signal Processing, Vol. 74, no. 3, 2013, pp. 545 – 556. DOI 10.1007/s10470-012-0002-x

  48. Uemura S., Hiraoka Y., Kai T., Dosho S.: Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs. IEEE Journal of Solid-State Circuits, Vol. 47, no. 4, 2012, pp. 810 – 816. DOI 10.1109/JSSC.2012.2185169

  49. Tagro Y., des Etangs-Levallois A., Lecavelier, Poulain L., Lepilliet S., Gloria D., Raynaud C., Dubois E., Danneville F.: High frequency noise potentialities of reported CMOS 65 nm SOI technology on flexible substrate. IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2012, pp. 89 – 92. DOI 10.1109/SiRF.2012.6160147

  50. Badami Komail M. H., Karmalkar S.: Quasi-Static Compact Model for Coupling Between Aligned Contacts on Finite Substrates With Insulating or Conducting Backplanes. IEEE Trans. on CAD of Integrated Circuits and Systems, 2012, Vol. 31, no 6, pp. 858 – 867. DOI 10.1109/TCAD.2012.2184106

  51. Nagata M.: Modeling and Analysis of Substrate Noise Coupling in Analog and RF Ics. IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences, 2012, Vol. E95A, no 2, pp. 430 – 438. DOI 10.1587/transfun.E95.A.430

  52. Gurugubelli V. K., Karmalkar S.: A scalable curve-fit model of the substrate coupling resistances for IC design. Proc of IEEE Int. Symp. on Quality Electronic Design, 2012, pp. 353 – 357. DOI 10.1109/ISQED.2012.6187517

  53. Stefanou A., G. Gielen: A Volterra Series Nonlinear Model of the Sampling Distortion in Flash ADCs Due to Substrate Noise Coupling. IEEE Trans on CAS II : Express Briefs, Vol. 58, no 12, 2011, pp 877 – 881. DOI 10.1109/TCSII.2011.2172714

  54. Azuma N., Kanda Y., Nagata M.: Extraction of lumped RC elements representing substrate coupling of RF devices. IEEE Radio Frequency Integrated Circuits Symp. (RFIC), 2011, pp. 217 – 220. DOI 10.1109/RFIT.2011.6141784

  55. Schroter P., Jahn S., Klotz F.: Improving the immunity of smart power integrated circuits by controlling RF substrate coupling. IEEE Int. Symp. on Electromagnetic Compatibility (EMC), 2011, pp. 45 – 50. DOI 10.1109/ISEMC.2011.6038282

  56. Sadiku M.N.O., Issa E.M., Attia J.O., Momoh O.D.: Substrate coupling in mixed signal integrated circuits. Proc. of IEEE Southeastcon, 2011, pp. 401 – 404. DOI 10.1109/SECON.2011.5752974

  57. Khan N.H., Alam S.M., Hassoun S.: Mitigating TSV-induced substrate noise in 3-D ICs using GND plugs. 12th Int. Symp. on Quality Electronic Design (ISQED), 2011, pp. 1 – 6. DOI 10.1109/ISQED.2011.5770813

  58. Xu C., Suaya R., Banerjee K.: Compact Modeling and Analysis of Through-Si-Via-Induced Electrical Noise Coupling in Three-Dimensional ICs. IEEE Trans. on Electron Devices, Vol. 58, no. 11, 2011, pp. 4024 – 4034. DOI 10.1109/TED.2011.2166156

  59. Koo Kyoungchoul, Kim Myunghoi, Lee Sangrok, Kim Joungho: Measurement and analysis of vertical noise coupling on low noise amplifier from on-chip switching-mode DC-DC converter in 3D-IC. IEEE Int. Symp. on Electromagnetic Compatibility (EMC), 2011, pp. 22 – 27. DOI 10.1109/ISEMC.2011.6038278

  60. Bronckers S., Van der Plas G., Vandersteen G., Rolain Y.: Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors. IEEE Trans on Instr. & Meas., Vol. 59, no 6, 2010, pp 1727 – 1733. DOI 10.1109/TIM.2009.2024370

  61. Mohamed C., Barelaud B., Ngoya E.: Physical analysis of substrate noise coupling in mixed circuits in SoC technology. 2010 European Microwave Integrated Circuits Conf (EuMIC), Vol., no., pp 274 – 277. ISBN: 978-1-4244-7231-4

  62. Park Chan Hyeong, Oh Yongho, Rieh Jae-Sung: Noise Figure Formulas of RF MOSFETs in the Presence of Digital Substrate Noise. Microwave and Wireless Components Letters, Vol. 20, no 11, 2010, pp 622 – 624. DOI 10.1109/LMWC.2010.2068041

  63. Yongho Oh, Sanggeun Jeon, Jae-Sung Rieh: Variation in RF Performance of MOSFETs Due to Substrate Digital Noise Coupling. Microwave and Wireless Components Letters, Vol. 20, no 7, 2010, pp 384 – 386. DOI 10.1109/LMWC.2010.2049431

  64. Kang I.M., Shin H: Extraction method for cross-type substrate resistances of RF MOSFETs based on PSP model. Electronics Lett., Vol. 46, no 11, 2010, pp 784 – 786. DOI 10.1049/el.2010.0763

  65. Stefanou A., G. Gielen: Analyzing and modeling the performance degradation of flash A/D converters due to substrate noise coupling. Analog Integr Circ Sig Process, Vol. 65, no 2, 2010, pp 185 – 195. DOI 10.1007/s10470-010-9475-7

  66. Jyh-Chyurn Guo,  Yi-Hsiu Tsai : A Broadband and Scalable Lossy Substrate Model for RF Noise Simulation and Analysis in Nanoscale MOSFETs With Various Pad Structures. IEEE Trans. on MTT, Vol. 57, no 2, 2009, pp 271 – 281. DOI 10.1109/TMTT.2008.2009903

  67. Stephane Bronckers, Karen Scheir, Geert Van der Plas, Gerd Vandersteen, Yves Rolain : A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems. IEEE Trans on CAD of Integrated Circuits and Systems, Vol. 28, no. 11, 2009, pp. 1613 – 1626. DOI 10.1109/TCAD.2009.2030360

  68. Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin : Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling. IEEE Trans on Very Large Scale Integration (VLSI) Systems, Vol. 17, no. 10, 2009, pp. 1559 – 1564. DOI 10.1109/TVLSI.2008.2005195

  69. Chan Hyeong Park, Jae-Sung Rieh, Yongho Oh, Seungyong Lee: Impact of Substrate Digital Noise Coupling on the High-Frequency Noise Performance of RF MOSFETs. IEEE Microwave and Wireless Components Letters, Vol. 19, no 9, 2009, pp 557 – 559. DOI 10.1109/LMWC.2009.2027064

  70. Nauman Khan, Syed Alam, Soha Hassoun: Through-Silicon Via (TSV)-Induced Noise Characterization And Noise Mitigation Using Coaxial TSVs. IEEE Int. 3D Systems Integration Conf. (3DIC), 2009, pp. 1 – 7. DOI 10.1109/3DIC.2009.5306579

  71. Shayan A., Xiang Hu, Wanping Zhang, Chung-Kuan Cheng, Engin A.E., Xiaoming Chen, Popovich M.: 3D stacked power distribution considering substrate coupling. IEEE Int. Conf. on Computer Design, ICCD 2009, pp 225 – 230. DOI 10.1109/ICCD.2009.5413151

  72. Crovetti P. S., Fiori F. : Efficient BEM-based substrate network extraction in silicon SoCs. Microelectronics J., Elsevier, Vol. 39, no 12, 2008, pp. 1774 – 1784., http://dx.doi.org/10.1016/j.mejo.2008.07.034

  73. V. Kilchytska, D. Flandre, J.-P. Raskin : Silicon-on-Nothing MOSFETs: An efficient solution for parasitic substrate coupling suppression in SOI devices. Applied Surface Science, Vol 254, 2008, pp 6168 – 6173. DOI 10.1016/j.apsusc.2008.02.171

  74. Chao H.-M., Wuen W.-S., Wen K.-A.: An Active Guarding Circuit Design for Wideband Substrate Noise Suppression. IEEE Trans on MTT, Vol. 56, no 11, part 2, 2008, pp 2609 – 2619. DOI 10.1109/TMTT.2008.2004900

  75. Salman E., Friedman E.G., Secareanu R.M., Hartin O.L.: Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates. 9th Int. Symp. on Quality Electronic Design (ISQED 2008), 2008, pp. 261 – 266. DOI 10.1109/ISQED.2008.4479736

  76. E. Backenius : Reduction of Substrate Noise in Mixed-Signal Circuits. Linköping Studies in Science and Technology, Dissertations, No. 1094. Department of Electrical Engineering Linköping University, SE-581 83 Linköping, Sweden, 2007 http://liu.diva-portal.org/smash/get/diva2:23520/FULLTEXT01

  77. Binet V., Savaria Y., Meunier M., Gagnon Y.: Modeling the Substrate Noise Injected by a DC-DC Converter. IEEE Int. Symp on Circuits and Systems (ISCAS), 2007, pp. 309 – 312. DOI 10.1109/ISCAS.2007.378397

  78. Comeau J.P., Najafizadeh L., Andrews J.M., Prakash A.P.G., Cressler J.D.: An Exploration of Substrate Coupling at K-Band Between a SiGe HBT Power Amplifier and a SiGe HBT Voltage-Controlled-Oscillator. IEEE Microwave and Wireless Components Letters, Vol. 17, no 5, 2007, pp 349 – 351. DOI 10.1109/LMWC.2007.895703

  79. Spiegel J., de la Torre J., Darques M., Piraux L., Huynen I.: Permittivity Model for Ferromagnetic Nanowired Substrates. IEEE Microwave and Wireless Components Letters, Vol. 17, no 7, 2007, pp 492 – 494. DOI 10.1109/LMWC.2007.899303

  80. Manetas G., Kourkoulos V.N., Cangellaris A.C.: Investigation on the Frequency Range of Validity of Electroquasistatic RC Models for Semiconductor Substrate Coupling Modeling. IEEE Trans on Electromagnetic Compatibility, Vol. 49, no 3, 2007, pp 577 – 584. DOI 10.1109/TEMC.2007.902387

  81. Jae-Hong Jung, Jong-Ho Lee: Extraction of Substrate Resistance in Bulk FinFETs Through RF Modeling. IEEE Microwave and Wireless Components Letters, Vol. 17, no 5, 2007, pp 358 – 360. DOI 10.1109/LMWC.2007.895709

  82. Hsien-Hung Wu, Chin-Hsin Fu, Yaw-Feng Wang, Pei-Wen Luo, Yen-Ming Chen, Liang-Chia Cheng, Cheng-Hsing Chien: Characterization of Supply and Substrate Noises in CMOS Digital Circuits. Int. Symp on VLSI Design, Autom and Test (VLSI-DAT 2007), 2007, pp. 1 – 4. DOI 10.1109/VDAT.2007.373256

  83. Mendez, M.A., Mateo, D., Rubio, A., Gonzalez J.L.: Analytical and experimental verification of substrate noise spectrum for mixed-signal ICs. IEEE Trans on CAS I, I, Vol. 52, no 8, Aug 2006, pp 1803 – 1815. DOI 10.1109/TCSI.2006.879065

  84. Ardalan S.: Substrate Noise suppression Techniques for Systems on Chip. 49th IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS '06), vol. 1, 2006, pp.xxxvii – xxxviii. DOI 10.1109/MWSCAS.2006.381974

  85. Descamps P., Barbier-Petot C., Biard C., Bardy S.: Performance comparison of substrate coupling effect between silicon and SOI substrates in RF-CMOS technology. Electronics Lett., Vol. 42, no 20, 2006, pp 1151 – 1152. DOI 10.1049/el:20061830

  86. Lan H., Chen T.W., Chui C.O., Nikaeen P., Kim J.W., Dutton R.W.: Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs. IEEE J. of SSC, Vol. 41, no 8, Aug 2006, pp 1817 – 1829. DOI 10.1109/JSSC.2006.877272

  87. H.-Y. Chen, K.-M. Chen, G.-W. Huang, C.-Y. Chang: An improved parameter extraction method of SiGe HBTs' substrate network. IEEE Microwave & Wireless Comp. Let., Vol. 16, no 6, June 2006, pp 321 – 323. DOI 10.1109/LMWC.2006.875630

  88. Hazenboom, S., Fiez T.S., Mayaram, K.: A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4-GHz LNAs. IEEE J. of SSC, Vol. 41, no 3, March 2006, pp 574 – 587. DOI 10.1109/JSSC.2006.869790

  89. Huo X., Chan P. C. H., Chen K. J., Luong H. C.: A Physical Model for On-Chip Spiral Inductors With Accurate Substrate Modeling. IEEE Trans on ED, Vol. 53, no. 12, Dec 2006, pp 2942 – 2949. DOI 10.1109/TED.2006.885091

  90. De Wilde, M., Meeus, W., Rombouts, P., Van Campenhout, J.: A simple on-chip repetitive sampling setup for the quantification of substrate noise. IEEE J. of SSC, Vol. 41, no 5, May 2006, pp 1062 – 1072. DOI 10.1109/JSSC.2006.872873

  91. Badaroglu, M., Wambacq P., Van der Plas G., Donnay S., Gielen G.G.E, De Man H.J.: Evolution of substrate noise generation mechanisms with CMOS technology scaling. IEEE Trans on CAS I, Vol. 53, no 2, Feb 2006, pp 296 – 305. DOI 10.1109/TCSI.2005.856049

  92. Weize Xu, Friedman E.G.: On-chip test circuit for measuring substrate and line-to-line coupling noise. IEEE J. of SSC, Vol. 41, no 2, Febr. 2006, pp 474 – 482. DOI 10.1109/JSSC.2005.862349

  93. Birrer P., Arunachalam S. K., Held M., Mayaram K., Fiez T. S.: Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs. IEEE Trans on CAS I, Vol. 53, no 12, 2006, pp 2578 – 2587. DOI 10.1109/TCSI.2006.885689

  94. Soens C., Van der Plas G., Wambacq P., Donnay S., Kuijk M.: Performance Degradation of LC-Tank VCOs by Impact of Digital Switching Noise in Lightly Doped Substrates. IEEE JSSC, Vol. 40, No 7, July 2005, pp 1472 – 1480. DOI 10.1109/JSSC.2005.847301

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