Try not to become a man of success but rather try to become a man of value”

 (Albert Einstein)

  1. Zhou Renyan, Liu Leibo, Yin Shouyi, Luo Ao, Chen Xinkai, Wei Shaojun: A WiSN node SoC with real-time image compressor and IEEE 802.15.4 MAC accelerator. Int. J. of Electronics, Vol. 101, no. 11, 2014, pp. 1580 – 1594. DOI 10.1080/00207217.2014.888773

  2. Torres J., El-Nozahi M., Amer A., et al.: Low Drop-Out Voltage Regulators: Capacitor-less Architecture Comparison. IEEE Circuits and Devices Magazine, Vol. 14, no. 2, 2014, pp. 6 – 26. DOI 10.1109/MCAS.2014.2314263

  3. Peesapati R., Sabat S.L., Karthik, K. P., Narasimhappa M., Giribabu N., Nayak J.: FPGA-based embedded platform for fiber optic gyroscope signal denoising. Int. J. of Circuit Theory and Applications, Vol. 42, no. 7, 2014, pp. 744 – 757. DOI 10.1002/cta.1883

  4. Bozorgzadeh B., Covey D.P., Howard C.D., Garris P.A., Mohseni P.: A Neurochemical Pattern Generator SoC With Switched-Electrode Management for Single-Chip Electrical Stimulation and 9.3 mu W, 78 pA(rms), 400 V/s FSCV Sensing. IEEE Journal of SSC, Vol. 49, no. 4, 2014, Special Issue: SI, pp. 881 – 895. DOI 10.1109/JSSC.2014.2299434

  5. Singh Pawan Kumar, Sharma Sanjay: Substrate Coupling of RF CMOS on Lightly Doped Substrate for Nanoscale Mixed-Signal Design. J. of Computational and Theoretical Nanoscience, Vol. 11, no. 4, 2014, pp. 1184 – 1188. DOI 10.1166/jctn.2014.3480

  6. Park Chang-Joon, Onabajo M., Silva-Martinez J.: External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4-4 MHz Range. IEEE Journal of SSC, Vol. 49, no. 2, 2014, pp. 486 – 501. DOI 10.1109/JSSC.2013.2289897

  7. Chen Wei-Ming, Chiueh Herming, Chen Tsan-Jieh, et al.: A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control. IEEE Journal of SSC, Vol. 49, no. 1 Special Issue: SI, 2014, pp. 232 – 247. DOI 10.1109/JSSC.2013.2284346

  8. Chang-Hyeon Lee, Kabalican L., Yan Ge, Kwantono H., Unruh G., Chambers M., Fujimori I: A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS. Symp. on VLSI Circuits (Digest & Technical Papers), 2014, pp.1 - 2 DOI 10.1109/VLSIC.2014.6858390

  9. Mereni L., Pepe D., Zito D.: Analyses and design of 95-GHz SoC CMOS radiometers for passive body imaging. Analog Integrated Circuits & Signal Processing, Vol. 77, no. 3 Special Issue: SI, 2013, pp. 373 – 383. DOI 10.1007/s10470-013-0194-8

  10. Abdelhalim K., Kokarovtseva L., Velazquez J.L.Perez, Genov R.: 915-MHz FSK/OOK Wireless Neural Recording SoC With 64 Mixed-Signal FIR Filters. IEEE Journal of SSC, Vol. 48, no. 10, 2013, pp. 2478 – 2493. DOI 10.1109/JSSC.2013.2272849

  11. Aminzadeh H.: MOSFET-only Two-Stage Operational Amplifiers with Miller Compensation: Design and Fabrication in Nano-Scale CMOS. J. of Circuits Systems & Computers, Vol. 22, no. 8, 2013, Article # 1350065. DOI 10.1142/S0218126613500655

  12. Peesapati R., Sabat S.L., Anumandla K.K., Kandyala P.K., Nayak J.: Design and implementation of a realtime co-processor for denoising Fiber Optic Gyroscope signal. Digital Signal Processing, Vol. 23, no. 5, 2013, pp. 1813 – 1825. DOI 10.1016/j.dsp.2013.04.010

  13. Seguin-Moreau N.: Latest generation of ASICs for photodetector readout. Nuclear Instruments & Methods in Physics Research: Section A - Accelerators Spectrometers Detectors and Associated Equipment, Vol. 718, 2013, pp. 173 – 179. DOI 10.1016/j.nima.2012.11.134

  14. Lai Xin-Quan, Xing Zhi-Qiang, Shi Ling-Feng, Liu Chen, Du Han-Xiao: Study of Signal Integrity for a Novel Stacked Cylindrical PoP Package. IEEE Int. Symp. on Advanced Packaging Materials (APM), Book Series: Int. Symp. on Advanced Packaging Materials-Processes, Properties & Interfaces, 2013. DOI 10.1109/ISAPM.2013.6510385

  15. Chew W.C., Cangellaris A.C., Schutt-Aine J., Braunisch H., Qian Z.G., Aydiner A.A, Aygun K., Jiang L.J., Ma Z.H., Meng L.L., Naeem M.: Fast and accurate multiscale electromagnetic modeling framework: An overview. IEEE 17th Workshop on Signal and Power Integrity (SPI), 2013 pp.1 – 4. DOI 10.1109/SaPIW.2013.6558315

  16. Savidis I., Kose S., Friedman E.G.: Power Noise in TSV-Based 3-D Integrated Circuits. IEEE Journal of SSC, Vol. 48, no. 2, 2013, pp 587 – 597. DOI 10.1109/JSSC.2012.2217891

  17. Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang: Embedding Repeaters in Silicon IPs for Cross-IP Interconnections. IEEE Trans on VLSI, Vol. 21, no. 3, 2013, pp. 597 – 601. DOI 10.1109/TVLSI.2012.2190434

  18. Takeuchi K., Shimada M., Sato T., Katsuki Y., Yoshikawa H., Matsushita H.: Spatial Distribution Measurement of Dynamic Voltage Drop Caused by Pulse and Periodic Injection of Spot Noise. IEEE Trans on VLSI, Vol. 21, no. 1, 2013, pp. 164 – 168. DOI 10.1109/TVLSI.2011.2180742

  19. Kyoungchoul Koo, Myunghoi Kim, Kim, J.J., Joungho Kim, Jiseong Kim: Vertical Noise Coupling From On-Chip Switching-Mode Power Supply in a Mixed-Signal Stacked 3-D-IC. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 3, no. 3, 2013, pp. 476 – 488. DOI 10.1109/TCPMT.2012.2219621

  20. Saniie J., Oruklu E., Yoon Sungjoon: System-on-Chip Design for Ultrasonic Target Detection Using Split-Spectrum Processing and Neural Networks. IEEE Trans on Ultrasonics, Ferroelectrics and Frequency Control, Vol. 59, no. 7 Special Issue: SI, 2012, pp. 1354 – 1368. DOI 10.1109/TUFFC.2012.2336

  21. Uemura S., Hiraoka Y., Kai T., Dosho S.: Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs. IEEE J. of SSC, Vol. 47, no. 4, 2012, pp. 810 – 816. DOI 10.1109/JSSC.2012.2185169

  22. S. Revathi, R.Radhika : Signal Integrity modeling for high-speed DDRx Using Chip-Package Board analysis. Int. Journal of Power Control Signal and Computation (IJPCSC), Vol. 3, no 1, 2012 ISSN: 0976-268X www.ijcns.com

  23. Oikawa R., Gope D., Jandhyala V.: Return-Path Extraction Technique for SSO Analysis of Low-Cost Wire-Bonding BGA Packages. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 2, no. 4, 2012, pp. 677 – 686. DOI 10.1109/TCPMT.2012.2187015

  24. Myunghoi Kim, Kyoungchoul Koo, Chulsoon Hwang, Yujeong Shim, Joungho Kim, Jonghoon Kim: A Compact and Wideband Electromagnetic Bandgap Structure Using a Defected Ground Structure for Power/Ground Noise Suppression in Multilayer Packages and PCBs. IEEE Trans on EMC, Vol. 54, no. 3, 2012, pp. 689 – 695. DOI 10.1109/TEMC.2012.2187662

  25. Hung-Chuan Chen, Chung-Hao Tsai, Tzong-Lin Wu: A Compact and Embedded Balanced Bandpass Filter With Wideband Common-Mode Suppression on Wireless SiP. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 2, no. 6, 2012, pp.1030 – 1038. DOI 10.1109/TCPMT.2012.2186451

  26. Takatani H., Tanaka Y., Oizono Y., Nabeshima Y., Okumura T., Sudo T., Sakai A., Uchiyama S., Ikeda H.: PDN impedance and noise simulation of 3D SiP with a widebus structure. IEEE 62nd Electronic Components and Technology Conf. (ECTC), 2012, pp. 673 – 677. DOI 10.1109/ECTC.2012.6248904

  27. Hung-Chuan Chen, Chung-Hao Tsai, Tzong-Lin Wu: A Compact and Embedded Balanced Bandpass Filter With Wideband Common-Mode Suppression on Wireless SiP. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 2, no. 6, 2012, pp. 1030 – 1038. DOI 10.1109/TCPMT.2012.2186451

  28. Alimenti F., Mezzanotte P., Tasselli G., Battistini A., Palazzari V., Roselli L.: Development of Low-Cost 24-GHz Circuits Exploiting System-in-Package (SiP) Approach and Commercial PCB Technology. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 2, no. 8, 2012, pp.1265 – 1274. DOI 10.1109/TCPMT.2012.2184111

  29. Stamatiadis C., Kalavrouziotis D., Pagano A., Morro R., Riccardi E., Stampoulidis L., Voigt K., Preve G.B., Moerl L., Kreissl J., Landles K., Duffy S., Avramopoulos H., Zimmermann L., Petermann K.: Photonic Provisioning Using a Packaged SOI Hybrid All-Optical Wavelength Converter in a Meshed Optical Network Testbed. Journal of Lightwave Technology, Vol. 30, no 18, 2012, pp. 2941 – 2947. DOI 10.1109/JLT.2012.2209172

  30. Sanming Hu, Yong-Zhong Xiong, Lei Wang, Rui Li, Jinglin Shi, Teck-Guan Lim: Compact High-Gain mmWave Antenna for TSV-Based System-in-Package Application. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 2, no 5, 2012, pp. 841 – 846. DOI 10.1109/TCPMT.2012.2188293

  31. Raj P.M., Sharma H., Mishra D., Murali K.P., Kyuhwan Han, Swaminathan, M., Tummala, R.R.: Nanomagnetics for High-Performance, Miniaturized Power, and RF Components [Nanopackaging]. IEEE Nanotechnology Magazine, Vol. 6, no 3, 2012, pp. 18 – 23. DOI 10.1109/MNANO.2012.2203878

  32. Xuequan Yu, Yadong Bai, Yan Zhou, Wei Bai, Lin Yang, Junxin Min: EMI study of high-speed IC package based on pin map. Asia-Pacific Symp. on Electromagnetic Compatibility (APEMC), 2012, pp. 305 – 308. DOI 10.1109/APEMC.2012.6237855

  33. Oizono Yoshiaki, Nabeshima Yoshitaka, Okumura Takafumi, Sudo Toshio, Sakai Atsushi, Uchiyama Shiro, Ikeda Hiroaki: PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structure. IEEE Int. 3D Systems Integration Conference (3DIC), 2012, pp. 1 – 2. DOI 10.1109/3DIC.2012.6263028

  34. Matsushima T., Asai R., Nishimoto T., Wada O.: Degradation of signal integrity due to package-common-mode resonance caused by external conductive noise in power supply system. Asia-Pacific Symp. on Electromagnetic Compatibility (APEMC), 2012, pp. 85 – 88. DOI 10.1109/APEMC.2012.6237999

  35. Benfica J., Bolzani Poehls L., Vargas F., Lipovetzky J., Lutenberg A., Garcia S.E.: Configurable platform for SoC combined tests of TID radiation, aging and EMI. Asia-Pacific Symp. on Electromagnetic Compatibility (APEMC), 2012, pp. 393 – 396. DOI 10.1109/APEMC.2012.6237989

  36. Zhenxian Liang, Puqi Ning, Wang F., Marlino L.: Reducing Parasitic Electrical Parameters with a Planar Interconnection Packaging Structure. 7th Int. Conf on Integrated Power Electronics Systems (CIPS), 2012, pp. 1 – 6. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6170650&isnumber=6170617

  37. Lee J.K., Stoffel N., Fite K.: Electronic packaging of sensors for lower limb prosthetics. IEEE 62nd Electronic Components and Technology Conf (ECTC), 2012, pp. 86 – 91. DOI 10.1109/ECTC.2012.6248811

  38. Chinq-Shiun Chiu, Hsiang-Hui Chang, Tzung-Han Wu, Shin-Fu Chen, Chieh-Chuan Chin, Wei-Kai Hong, Sheng Jau Wong, Li-Shin Lai, Chi-Hsueh Wang, Song-Yu Yang, Ta-Hsin Lin, Jhy-Rong Chen, Hung-Chieh Tsai, Hsi-Ming Yang, Hsiao-Wei Chen, Marques A., Caiyi Wang, Chien G.: A 65nm GSM/GPRS/EDGE SoC with Integrated BT/FM. IEEE Radio Frequency Integrated Circuits Symp. (RFIC), 2012, pp. 403 – 406. DOI 10.1109/RFIC.2012.6242309

  39. Chandrashekar K., Pellerano S., Madoglio P., Ravi A., Palaskas Y.: A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management. IEEE Int. Solid-State Circ. Conf. Digest of Technical Papers (ISSCC), 2012, pp. 352 – 354. DOI 10.1109/ISSCC.2012.6177048

  40. Yuan Liang: RF NMOS switch, front end, up converted mixer, LC-VCO co-design in a SoC-based sensor chip in 0.13μm CMOS. Int. Conf. on System Science and Engineering (ICSSE), 2012, pp. 389 – 394. DOI 10.1109/ICSSE.2012.6257214

  41. Minchul Shin, Myunghoi Kim, Kyoungchoul Koo, Sunkyu Kong, Joungho Kim : Design and experimental verification of on-chip signal integrity analyzer (OSIA) scheme for eye diagram monitoring of a high-speed serial link. IEEE Int. Symp. on Electromagnetic Compatibility (EMC), 2011, pp. 119 – 125. DOI 10.1109/ISEMC.2011.6038295

  42. Wu Boping, Mo Tingting : Printed circuit board electrical design for wafer-level packaging. 12th Int. Conf. on Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2011, pp. 1 – 4. DOI 10.1109/ICEPT.2011.6066808

  43. Kyoungchoul Koo, Myunghoi Kim, Sangrok Lee, Joungho Kim : Measurement and analysis of vertical noise coupling on low noise amplifier from on-chip switching-mode DC-DC converter in 3D-IC. IEEE Int. Symp. on Electromagnetic Compatibility (EMC), 2011, pp. 22 – 27. DOI 10.1109/ISEMC.2011.6038278

  44. Bumhee Bae, Yujeong Shim, Jonghyun Cho, Joungho Kim : Simultaneous switching noise coupling through via transition for a CMOS negative feedback Operational Amplifier in System-in-Package. IEEE 54th Int. Midwest Symp. on Circuits and Systems (MWSCAS), 2011, pp 1 – 4. DOI 10.1109/MWSCAS.2011.6026494

  45. Sasaki H., Tsukuda T., Fujimura Y., Murakami T., Terai H. : Investigation of noise coupling in mixed-signal system-in-packages (SiPs). 8th Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo), 2011, pp.194 – 197.

  46. Bencivinni M., Camarda F., Capriglione D., Chiariello A.G., Fusillo G., Girardi A., Izzi R., Maffucci A., Martines I.: Characterization and modeling of the electromagnetic behavior of ICs and packages. Int. Conf. on Electromagnetics in Advanced Applications (ICEAA), 2011, pp. 1368 – 1371. DOI 10.1109/ICEAA.2011.6046276

  47. Mohajer-Iravani B., Ramahi O.M.: Reactive power radiated from the planar electromagnetic bandgap structures, a source of EMI in high speed packages. IEEE Int. Symp. on Antennas and Propagation (APSURSI), 2011, pp. 1840 – 1843. DOI 10.1109/APS.2011.5996855

  48. Guan-Zong Wu, Yi-Che Chen, Tzong-Lin Wu : Design and Implementation of a Novel Hybrid Photonic Crystal Power/Ground Layer for Broadband Power Noise Suppression. IEEE Trans. on Advanced Packaging, Vol. 33, no. 1, 2010, pp 206 – 211. DOI 10.1109/TADVP.2009.2034334

  49. Ndip I., Ohnimus F., Löbbicke K., Bierwirth M., Tschoban C., Guttowski S, Reichl H., Lang K.-D., Henke H.: Modeling, Quantification, and Reduction of the Impact of Uncontrolled Return Currents of Vias Transiting Multilayered Packages and Boards. IEEE Trans on EMC, Vol. 52, no 2, 2010, pp 421 – 435. DOI 10.1109/TEMC.2010.2049069

  50. Hao-Hsiang Chuang, Wei-Da Guo, Yu-Hsiang Lin, Hsin-Shu Chen, Yi-Chang Lu, Yung-Shou Cheng, Ming-Zhang Hong, Chun-Huang Yu, Wen-Chang Cheng, Yen-Ping Chou, Chuan-Jen Chang, Ku Joseph, Tzong-Lin Wu, Ruey-Beei Wu: Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Coanalysis. IEEE Trans on EMC, Vol. 52, no 2, 2010, pp 381 – 391. DOI 10.1109/TEMC.2010.2043108

  51. Tzong-Lin Wu, Hao-Hsiang Chuang, Ting-Kuang Wang: Overview of Power Integrity Solutions on Package and PCB: Decoupling and EBG Isolation. IEEE Trans on EMC, Vol. 52, no 2, 2010, pp 346 – 356. DOI 10.1109/TEMC.2009.2039575

  52. Guo-Ping Zou, Er-Ping Li, Xing-Chang Wei, Guang-Xiao Luo, Xiang Cui: A New Hybrid Field-Circuit Approach to Model the Power–Ground Planes With Narrow Slots. IEEE Trans on EMC, Vol. 52, no 2, 2010, pp 340 – 345. DOI 10.1109/TEMC.2010.2042604

  53. Kollia V., Cangellaris A.C.: A Domain Decomposition Approach for Efficient Electromagnetic Analysis of the Power Distribution Network of Packaged Electronic Systems. IEEE Trans on EMC, Vol. 52, no 2, 2010, pp 320 – 331. DOI 10.1109/TEMC.2010.2045380

  54. Hyun Ho Park, Seung-Hyun Song, Sang-Tae Han, Tae-Sun Jang, Jin-Hwan Jung, Hark-Byeong Park: Estimation of Power Switching Current by Chip-Package-PCB Cosimulation. IEEE Trans on EMC, Vol. 52, no 2, 2010, pp 311 – 319. DOI 10.1109/TEMC.2010.2043255

  55. Er-Ping Li, Xing-Chang Wei, Cangellaris A.C., En-Xiao Liu, Yao-Jiang Zhang, D'Amore M., Joungho Kim, Sudo Toshio: Progress Review of Electromagnetic Compatibility Analysis Technologies for Packages, Printed Circuit Boards, and Novel Interconnects. IEEE Trans on EMC, Vol. 52, no 2, 2010, pp 248 – 265. DOI 10.1109/TEMC.2010.2048755

  56. Hao-Hsiang Chuang, Chih-Jung Hsu, Hong J., Chun-Huang Yu, Cheng A., Ku J., Tzong-Lin Wu: A Broadband Chip-Level Power-Bus Model Feasible for Power Integrity Chip-Package Codesign in High-Speed Memory Circuits. IEEE Trans on EMC, Vol. 52, no 1, 2010, pp 235 – 239. DOI 10.1109/TEMC.2009.2035614

  57. Dajiang Yang, Yuanli Ding, Samny Huang: A 65-nm High-Frequency Low-Noise CMOS-Based RF SoC Technology. IEEE Trans on ED, Vol. 57, no 1, 2010, pp 328 – 335. DOI 10.1109/TED.2009.2034994

  58. Shapiro A.A., Tudryn C., Schatzel D., Tseng S.: Electronic Packaging Materials for Extreme, Low Temperature, Fatigue Environments. IEEE Trans. on Advanced Packaging, Vol. 33, no. 2, 2010, pp. 408 – 420. DOI 10.1109/TADVP.2010.2044504

  59. Bronckers S., Vandersteen G., De Locht L., Libois M., Van der Plas G., Rolain Y.: Experimental Analysis of the Coupling Mechanisms Between a 4 GHz PPA and a 5–7 GHz VCO. IEEE Trans on Instr. & Meas., Vol. 58, no 8, 2009, pp 2706 – 2713. DOI 10.1109/TIM.2009.2015705

  60. Yujeong Shim, Jongbae Park, Jaemin Kim, Eakhwan Song, Jeongsik Yoo, Junso Pak, Joungho Kim : Modeling and Analysis of Simultaneous Switching Noise Coupling for a CMOS Negative-Feedback Operational Amplifier in System-in-Package. IEEE Trans on EMC, Vol. 51, no 3, part 2, 2009, pp 763 – 773. DOI 10.1109/TEMC.2009.2026637

  61. Zaw Zaw Oo, En-Xiao Liu, Er-Ping Li, Xingchang Wei, Yaojiang Zhang, Mark Tan, Le-Wei Joshua Li, Rudiger Vahldieck : A semi-analytical approach for system-level electrical modeling of electronic packages with large number of vias. IEEE Trans. on Advanced Packaging, Vol. 31, no. 2, 2008, pp. 267 – 274. DOI 10.1109/TADVP.2008.923379

  62. Xingchang Wei, Er-Ping Li, En-Xiao Liu, Eng-Kee Chua, Zaw Zaw Oo, R. Vahldieck : Emission and susceptibility modeling of finite-size power-ground planes using a hybrid integral equation method. IEEE Trans. on Advanced Packaging, Vol. 31, no. 3, 2008, pp. 536 – 543. DOI 10.1109/TADVP.2008.927841

  63. Jiwoo Pak, Myunghyun Ha, Jaemin Kim, Donghee Kang, Ho Choi, Seyoung Kwon, Keunsoo La, Joungho Kim : Design of a 3-D SiP for T-DMB with Improvement of Sensitivity and Noise Isolation. 10th Electronics Packaging Technology Conf. (EPTC), Singapore, 2008, pp 1387 – 1392. DOI 10.1109/EPTC.2008.4763625

  64. Sankaran N., Huh S., Swaminathan M., Tummala R.: 2008 IEEE electrical performance of electronic packaging Suppression of Vertical Coupling using Electromagnetic Band Gap Structures. IEEE Electrical Performance of Electronic Packaging, 2008, pp 173 – 176. DOI: 10.1109/EPEP.2008.4675906

  65. Scogna A.C.: SSN mitigation by means of a 2D EBG structure with square patches and meander lines. Electrical Performance of Electronic Packaging, 2008, pp 43 – 46. DOI 10.1109/EPEP.2008.4675872

  66. Iorga C.: Understanding and effectively suppressing the noise coupling in mixed-signal SOC applications. 2008 IEEE Int. SOC Conf., 17-20 Sept. 2008, p 391. DOI 10.1109/SOCC.2008.4641554  

  67. R.-B. Sun, C.-M. Lin, R.-B. Wu: Designs of signal-ground bump-patterns for minimizing the simultaneous switching noise in a ball grid array. Electrical Performance of Electronic Packaging, 2008, pp 15 – 18. DOI: 10.1109/EPEP.2008.4675864

  68. Y. Hu, J. Chen, Lamson M., Bashirullah R.: An active crosstalk reduction technique for parallel high-speed links in low cost wirebond BGA packages. Electrical Performance of Electronic Packaging, 2008, pp 37 – 40. DOI: 10.1109/EPEP.2008.4675870

  69. Jiang L., Kolluri S., Rubin B.J., Smith H., Colgan E.G., Scheuermann M.R., Wakil J.A., Deutsch A., Gill J.: Thermal modeling of on-chip interconnects and 3D packaging using EM tools. Electrical Performance of Electronic Packaging, 2008, pp 279 – 282. DOI: 10.1109/EPEP.2008.4675934

  70. Kobayashi N., Morishita K., Harada T.: Analysis of EBG structures using SPICE models of multiple planes. Electrical Performance of Electronic Packaging, 2008, pp 111 – 114. DOI: 10.1109/EPEP.2008.4675890

  71. E. B. Liao, Hongyu Li, L. H. Guo, Guo-Qiang (Patrick) Lo, Rakesh Kumar, N. Balasubramanian, Dim-Lee Kwong: RF, DC, and Reliability Performance of MIM Capacitors Embedded in Organic Substrates by Wafer-Transfer Technology (WTT) for System-on-Package Applications. IEEE Trans on ED, Vol. 54, no 3, 2007, pp 425 – 432. DOI 10.1109/TED.2006.890233

  72. Arabi K., Saleh R., Meng Xiongfei: Power Supply Noise in SoCs: Metrics, Management, and Measurement. IEEE Design & Test of Computers, Vol. 24, no 3, May-June 2007, pp 236 – 244. DOI: 10.1109/MDT.2007.79

  73. Iorga C., Yi-Chang Lu, Dutton R.W.: A Built-in Technique for Measuring Substrate and Power-Supply Digital Switching Noise Using PMOS-Based Differential Sensors and a Waveform Sampler in System-on-Chip Applications. IEEE Trans on Instr. & Meas., Vol. 56, no 6, 2007, pp 2330 – 2337. DOI 10.1109/TIM.2007.908603

  74. Falk H.: Prolog to Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation. Proc of the IEEE, Vol. 94, no 12, December 2006, pp 2107 – 2108. DOI: 10.1109/JPROC.2006.886024

  75. Jongbae Park, Lu A.C.W., Chua K.M., Wai L.L., Junho Lee, Joungho Kim: Double-Stacked EBG Structure for Wideband Suppression of Simultaneous Switching Noise in LTCC-Based SiP Applications. IEEE Microwave and Wireless Components Letters, Vol. 16, no 9, 2006, pp 481 – 483. DOI 10.1109/LMWC.2006.880719

  76. Youchul Jeong, Lu A.C.W., Wai L.L., Wei Fan, Lok B.K., Hyunjeong Park, Joungho Kim: Hybrid analytical modeling method for split power bus in multilayered package. IEEE Trans on EMC, Vol. 48, no 1, 2006, pp 82 – 94. DOI 10.1109/TEMC.2006.870701

  77. Pfeiffer U.R., Grzyb J., Liu D., Gaucher B., Beukema T., Floyd B.A., Reynolds S.K. : A chip-scale packaging technology for 60-GHz wireless chipsets. IEEE Trans on MTT, Vol. 54, no 8, 2006, pp 3387 – 3397. DOI 10.1109/TMTT.2006.877832

  78. Sakamoto N., Sugita N., Kikuchi T., Tanaka H., Akazawa T.: Designing and packaging technology of Renesas SIP. IEEE Int. Symp on Circuits and Systems (ISCAS), Vol. 6, 2005, pp.5926 – 5929. DOI 10.1109/ISCAS.2005.1465988

  79. T.-L. Hsu, Y.-C. Chen, H.-C. Tseng, Liang V., Jan J.S.: Psub guard ring design and modeling for the purpose of substrate noise isolation in the SOC era. IEEE ED Lett., Vol. 26, no 9, September 2005, pp 693 – 695. DOI: 10.1109/LED.2005.854351

  80. Hyunjeong Park, Hyungsoo Kim, Dong Gun Kam, Joungho Kim : Co-Modeling and Co-Simulation of Package and On-Chip Decoupling Capacitor for Resonant Free Power/Ground Network Design. Proc. of 55th Electronic Components and Technology Conf., 2005, pp 727 – 731. DOI 10.1109/ECTC.2005.1441350

  81. K. Chong, X. Zhang, K.-N. Tu, D.Huang, M.-C. Chang, Y.-H. Xie: Three-dimensional substrate impedance engineering based on p/sup -//p/sup +/ Si substrate for mixed-signal system-on-chip (SoC). IEEE Trans on ED, Vol. 52, no. 11, November 2005, pp 2440 – 2446. DOI 10.1109/TED.2005.857190

  82. Nagata M., Okumoto T., Taki K.: A Built-in Technique for Probing Power Supply and Ground Noise Distribution Within Large-Scale Digital Integrated Circuits. IEEE JSSC, Vol. 40, no 4, April 2005, pp 813 819. DOI 10.1109/JSSC.2005.845559

  83. Becer M., Vaidyanathan R., Oh C., Panda R.: Crosstalk noise control in an SoC physical design flow. IEEE Trans on CAD of IC & Syst., Vol 23, no 4, April 2004, pp 488 – 497. DOI: 10.1109/TCAD.2004.825855

  84. T.-S. Chen, C.-Y. Lee, C.-H. Kao: An efficient noise isolation technique for SOC application. IEEE Trans on ED, Vol 51, no 2, February 2004, pp 255 – 260. DOI: 10.1109/TED.2003.821565

  85. Tsukada T., Hashimoto Y., Sakata K., Okada H., Ishibashi K.: An On-Chip Active Decoupling Circuit to Suppress Crosstalk in Deep-Submicron CMOS Mixed-Signal SoCs. IEEE JSSC, Vol 40, No 1, Jan. 2004, pp 67 – 79. DOI 10.1109/JSSC.2004.838010

  86. Swaminathn M., Kim J., Novak I., Libous J.: Power distribution networks for system-on-package: status and challenges. IEEE Trans. Adv. Packag. Vol. 27, no 2, 2004, pp. 286 – 300. DOI 10.1109/TADVP.2004.831897

  87. Tehranipour M.H., Ahmed N., Nourani M. : Testing SoC interconnects for signal integrity using extended JTAG architecture. IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 23, no. 5, 2004, pp. 800 – 811. DOI 10.1109/TCAD.2004.826540

  88. Grivet-Talocia S.: Package Macromodeling via Time-Domain Vector Fitting. IEEE Microwave & Wireless Comp Let, Vol 13, No 11, Nov. 2003, pp 472 – 474. DOI 10.1109/LMWC.2003.819378

  89. Khan Z., Erdogan A.T., Arslan T.: Dual low-power and crosstalk immune encoding scheme for on-chip data buses. Electronics Lett., Vol. 39, no 20, 2003, pp 1436 – 1437. DOI 10.1049/el:20030934

  90. J. He, D. Zhong, S. Y. Ji, G. Li, Y.-L. Li: Study of package EMI reduction for GHz microprocessors. Electrical Performance of Electronic Packaging, 2002, pp 271 – 274. DOI: 10.1109/EPEP.2002.1057930

  91. Sakalas P., Zirath H., Litwin A, Schröter M., Matulionis A.: Impact of Pad and Gate Parasitics on Small-Signal and Noise Modeling of 0.35 m Gate Length MOS Transistors. IEEE Trans. on ED, Vol. 49, no. 5, May 2002, pp 871 – 879. DOI 10.1109/16.998597

  92. Choi J., Swaminathan M., Do N., Master R.: Modeling of power supply noise in large chips with nonlinear circuits. Electrical Performance of Electronic Packaging, 2002, pp 257 – 260. DOI: 10.1109/EPEP.2002.1057927

  93. Li-Fu Chang, K.-J. Chang: Accurate and efficient inductance extraction for SoC noise and signal integrity. Electrical Performance of Electronic Packaging, IEEE 11th Topical Meeting on Electrical Performance of Electronic Packaging, 2002, pp 209 – 213. DOI: 10.1109/EPEP.2002.1057917

  94. Kelander I., Arslan A., Hurskainen V.: Modeling of spiral and meander lines in multilayer passive integration. Electrical Performance of Electronic Packaging, 2002, pp 83 – 86. DOI: 10.1109/EPEP.2002.1057888

  95. Swenson D.: ANSI/ESD S541: ESDA Releases Critical New Packaging Standard. http://www.ce-mag.com/archive/04/Swenson.html

  96. Evans R.J., White D.B., Pomerleau R., Scougal A.: Control of SSO noise through the use of on-chip decoupling cells. Electrical Performance of Electronic Packaging, 2002, pp 201 – 204. DOI: 10.1109/EPEP.2002.1057915

  97. Z. Chen: Separated transmission and noise models for coupled lines and connectors in packaging system timing and coupled noise simulations. Electrical Performance of Electronic Packaging, 2002, pp 305 – 308. DOI: 10.1109/EPEP.2002.1057938

  98. Dangelmayer T., Welsher T.: ESD Packaging Considerations. http://www.ce-mag.com/archive/03/09/dangelmayer.htm

  99. Kaw R., Hanna B., Devnani N.: Comparison of electrical performance of enhanced BGA's. IEEE Trans on Comp., Packaging and Manufacturing Technology. Part B: Advanced Packaging, Vol 21, no 2, 1998, pp 164 – 170. DOI: 10.1109/96.673704

  100. Bedouani M.: High density integrated circuit design: simultaneous switching ground/power noises calculation for pin grid array packages. Proc of 43rd Electronic Components and Technology Conference, 1993, pp 1039. DOI 10.1109/ECTC.1993.346724

  101. Prince J.L., Senthinathan R.: Simultaneous Switching Ground Noise Calculation for Packaged CMOS Devices. IEEE J of SSC, Vol. 26, no 11, Nov 1991, pp 1724 – 1728. DOI 10.1109/4.98995

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