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INTERFERENCE in SOC, SIP and PACKAGES

Try not to become a man of success, but rather try to become a man of value”

 (Albert Einstein)

  1. Pandey Bishwajeet, Das Bhagwan, Kaur Amanpreet, et al.: Performance Evaluation of FIR Filter After Implementation on Different FPGA and SOC and Its Utilization in Communication and Network. Wireless Personal Communications, Vol. 95, no. 2, 2017, pp. 375 – 389. DOI 10.1007/s11277-016-3898-0

  2. Whatmough P.N., Das Shidhartha, Hadjilambrou Z., et al.: Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor. IEEE Journal of Solid State Circ., Vol. 52, no. 6, 2017, pp. 1643 – 1654. DOI 10.1109/JSSC.2017.2669025

  3. Tan X., Li X.C., Mao J.: Time-Domain Analysis of Noise Coupling Between Package and PCB Power/Ground Planes Based on WLP-FDTD. IEEE Trans on Components, Packaging & Manufacturing Technology, Vol. 7, no. 2, 2017, pp. 269 – 275. DOI 10.1109/TCPMT.2016.2628050

  4. Shih Yu-Ju, Huang Chih-Tsun, Liou Jing-Jia, et al.: Optimization for Application-Specific Packet-Based On-Chip Interconnects Using a Cycle-Accurate Model. Int. Symp. on VLSI Design, Automation and Test (VLSI-DAT), 2017. DOI 10.1109/VLSI-DAT.2017.7939676

  5. Xu G., Gai W., Luo L., Zhang S., Xie X.: Influence of packaging effects on the mobile noise of planar SQUID gradiometer for airborne magnetic measurements. 18th Int. Conf. on Electronic Packaging Technology (ICEPT), 2017, pp. 1529 – 1532. DOI 10.1109/ICEPT.2017.8046726

  6. Bourgeois P.Y., Goavec-Merou G., Friedt J.M., Rubiola E.: A fully-digital realtime SoC FPGA based phase noise analyzer with cross-correlation. Joint Conf. of the European Frequency and Time Forum and IEEE Int. Frequency Control Symp. (EFTF/IFC), 2017, pp. 578 – 582. DOI 10.1109/FCS.2017.8088963

  7. Stal S.M., Scholz K., Bandyopadhyay T., et al.: Deep Dive into DDR3 Interface Jitter Contributors. 21st IEEE Workshop on Signal and Power Integrity (SPI), 2017.

  8. Ko Baekseok, Kim Joowon, Ryoo Jaemin, et al.: Simplified Chip Power Modeling Methodology Without Netlist Information in Early Stage of SoC Design Process. IEEE Trans on Components, Packaging & Manufacturing Technology, Vol. 6, no. 10, 2016, pp. 1513 – 1521. DOI 10.1109/TCPMT.2016.2599541

  9. Nomura Takao, Mori Ryo, Takayanagi Koji, et al.: Design Challenges 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM. IEEE Journal of Emerging & Selected Topics in Circuits and Systems, Vol. 6, no. 3, 2016, pp. 364 – 372. DOI 10.1109/JETCAS.2016.2547719

  10. Chu Zhufei, Xia Yinshui, Wang Lunyao, et al.: Efficient power pad assignment for multi-voltage SoC and its application in floorplanning. Int. J. of Circuit Theory and Applications, Vol. 44, no. 8, 2016, pp. 1533 – 1550. DOI 10.1002/cta.2178

  11. Shim Yujeong, Oh Dan: System Level Modeling of Timing Margin Loss Due to Dynamic Supply Noise for High-Speed Clock Forwarding Interface. IEEE Trans on EMC, Vol. 58, no. 4, Special Issue: SI, Part: 2, 2016, pp. 1349 – 1358. DOI 10.1109/TEMC.2016.2574720

  12. Noulis T., Merakos P., Lourandakis E., et al.: Wide-band substrate crosstalk sensor for wireless SoC applications. Sensors & Actuators A - Physical, Vol. 239, 2016, pp. 144 – 152. DOI 10.1016/j.sna.2016.01.014

  13. Feng Tao, Lajnef Nizar, Chakrabartty Shantanu: Design of a CMOS System-on-Chip for Passive, Near-Field Ultrasonic Energy Harvesting and Back-Telemetry. IEEE Trans on VLSI Systems, Vol. 24, no. 2, 2016, pp. 544 – 554. DOI 10.1109/TVLSI.2015.2401037

  14. Han Y., Huynh H.A., Kim S.: A new pinwheel meander-perforated plane structure for noise suppression in system-on-package. IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2016, pp. 123 – 125. DOI 10.1109/EDAPS.2016.7893142

  15. Chu F.C., Kuo H.C., Wang C.C.: Lowering coupling noise between chips in System-in-Package (SiP) module using compartment shielding. 11th Int. Microsystems, Packaging, Assembly and Circuits Technology Conf. (IMPACT), 2016, pp. 152 – 155. DOI 10.1109/IMPACT.2016.7800068

  16. Huh S.L., Shi H.: Detection of Noise Coupling between Power Domains on Package. IEEE 66th Electronic Components and Technology Conf. (ECTC), 2016, pp. 2028 – 2033. DOI 10.1109/ECTC.2016.378

  17. Hasegawa T., Toshiki Kanamoto, Hiroaki Ammo, Masaharu Kawano, et al.: A new EMI-noise reduction method in LSI-Package-Board system. IEEE 20th Workshop on Signal and Power Integrity (SPI), 2016, pp. 1-4. DOI 10.1109/SaPIW.2016.7496267

  18. Batra S., Singh P., Kaushik S., Hashmi M.S.: Frequency domain analysis of on-chip power distribution network. 20th Int. Symp. on VLSI Design and Test (VDAT), 2016, pp. 1 – 6. DOI 10.1109/ISVDAT.2016.8064853

  19. Zhu Qi, Venkataraman Srikrishnan, Ye Chunfei, et al.: Package Design Challenges and Optimizations in Density Efficient (Intel (R) Xeon (R) Processor D) SoC. IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2016. DOI 10.1109/EDAPS.2016.7893122

  20. Li Ming, Tang Tony, Chen Jie, et al.: Silicon-Package Co-Design of a 45nm 200MHz Bandwidth CMOS RF-to-Serdes Transceiver System on Chip (SoC). 25th IEEE Conf on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2016, pp. 7 – 9. DOI 10.1109/EPEPS.2016.7835406

  21. Majeric F., Bturbat E., Bossuet L.: Electromagnetic security tests for SoC. 23rd IEEE Int. Conf. on Electronics, Circuits and Systems (ICECS), 2016, pp. 265 – 268. DOI 10.1109/ICECS.2016.7841183

  22. Chen Nan-Cheng, Wu Wen Zhou, LSheng-Mou, et al.: A highly integrated RFSoC design for 3G smart phone application. 66th IEEE Electronic Components and Technology Conf. (ECTC), 2016, pp. 1309 – 1315. DOI 10.1109/ECTC.2016.37

  23. Chakraborty M., Chakrabarti A., Mitra P., Saha D., Guha K.: Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC. 20th Int. Symposium on VLSI Design and Test (VDAT), 2016, pp. 1 – 6. DOI 10.1109/ISVDAT.2016.8064873

  24. Gavriilidou V., Noulis T., Siskos S.: Substrate noise simulation for high frequency CMOS system on chip design. 5th Int. Conf. on Modern Circuits and Systems Technologies (MOCAST), 2016, pp. 1 – 4. DOI 10.1109/MOCAST.2016.7495129

  25. Agarwal N., Agarwal N., Sharma M.K.: Design a test chip to find out mixed signal interference with broad range instrumentation amplifier. 5th Int. Symp. on Next-Generation Electronics (ISNE), 2016, pp. 1 – 2. DOI 10.1109/ISNE.2016.7543366

  26. Sehgal Vivek Kumar: Markovian Models Based Stochastic Communication in Networks-in-Package. IEEE Trans on Parallel & Distributed Systems, Vol. 26, no. 10, 2015, pp. 2806 – 2821. DOI 10.1109/TPDS.2014.2358218

  27. Noulis T., Lourandakis E., Stefanou S., Merakos P.: CMOS 65 nm 'on chip' broadband real time substrate noise measurement. Electronics Lett., Vol. 51, no. 21, 2015, pp. 1710 – 1711. DOI 10.1049/el.2015.2099

  28. Wang X., Jiang Xu, Wei Zhang, et al.: Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories MPSoC. IEEE Trans on VLSI Systems, Vol. 23, no. 2, 2015, pp. 266 – 279. DOI 10.1109/TVLSI.2014.2306959

  29. Wang C.T., Jeng-Shien Hsieh, Victor C.Y.Chang, et al.: Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology. Int. 3D Systems Integration Conf. (3DIC), 2015, pp. TS6.3.1 – TS6.3.4. DOI 10.1109/3DIC.2015.7334573

  30. Aw C.H., Quek L.C., Shu H.C.: Silicon level circuit implementation for system-on-chip power integrity improvement. Int. Conf. on Electronics Packaging and iMAPS All Asia Conf. (ICEP-IAAC), 2015, pp. 748 – 751. DOI 10.1109/ICEP-IAAC.2015.7111109

  31. Peng Y.J., Chen Y.J.,Tu M.H., Wu S.M., Chen C.C.: A real-time simultaneous switching noise analysis by near-field measurement system for BGA package. Asia-Pacific Microwave Conf. (APMC), 2015, pp. 1 – 3. DOI 10.1109/APMC.2015.7411737

  32. Zhang X., Tong T., Brooks D., Wei G.Y.: Evaluating Adaptive Clocking for Supply-Noise Resilience in Battery-Powered Aerial Microrobotic System-on-Chip. IEEE Trans on Circuits and Systems I: Regular Papers, Vol. 61, no. 8, 2014, pp. 2309 – 2317. DOI 10.1109/TCSI.2014.2312490

  33. Shiue G.H., Yeh C.L., Huang P.W., Liao H.Y., Zhang Z.H.: Ground Bounce Noise Induced by Crosstalk Noise for Two Parallel Ground Planes With a Narrow Open-Stub Line and Adjacent Signal Traces Multilayer Package Structure. IEEE Trans on Components, Packaging & Manufacturing Technology, Vol. 4, no. 5, 2014, pp. 870 – 881. DOI 10.1109/TCPMT.2014.2299281

  34. Wu Y., Hao Z., Han J., Tsai J.: A novel power noise simulation methodology for chip design using Wafer Level Chip Scale Packaging. Technical Papers of Int. Symposium on VLSI Design, Automation and Test, 2014, pp. 1 – 4. DOI 10.1109/VLSI-DAT.2014.6834875

  35. Song E., Kim H., Kim J.J., Song C., Lee H., Kim J.: Reductions power noise and system area burden using wireless power transfer scheme in 3D package. IEEE Wireless Power Transfer Conf., 2014, pp. 178 – 181. DOI 10.1109/WPT.2014.6839576

  36. Kiyoshige S., Ichimura W., Sudo T.: Study on power supply noise and electromagnetic radiation in relation to chip-package anti-resonance. IEEE Electrical Design of Advanced Packaging & Systems Symp. (EDAPS), 2014, pp. 89 – 92. DOI 10.1109/EDAPS.2014.7030814

  37. Wei X.C., Wei X., Li Y.S., Zhang J.B., Li E.P., Dai G.L.: The application of high impedance surface for noise reduction inside the package. IEEE Int. Symp. on Electromagnetic Compatibility (EMC), 2014, pp. 428 – 432. DOI 10.1109/ISEMC.2014.6899010

  38. Baek H., Eisenstadt W.R.: Characterization of on-die power supply noise in FCBGA (Flip-chip ball grid array) packages. IEEE 64th Electronic Components and Technology Conf. (ECTC), 2014, pp. 554 – 559. DOI 10.1109/ECTC.2014.6897339

  39. Santriaji M.H., Mauludin H., Surgawiwaha D., Adiono T.: Real-time implementation of Maximum a Posteriori (MAP) based noise reductions using Leon 3 System on Chip. Int. Conf. on Electrical Engineering and Computer Science (ICEECS), 2014. DOI 10.1109/ICEECS.2014.7045216

  40. Zhou Renyan, Liu Leibo, Yin Shouyi, Luo Ao, Chen Xinkai, Wei Shaojun: A WiSN node SoC with real-time image compressor and IEEE 802.15.4 MAC accelerator. Int. J. of Electronics, Vol. 101, no. 11, 2014, pp. 1580 – 1594. DOI 10.1080/00207217.2014.888773

  41. Torres J., El-Nozahi M., Amer A., et al.: Low Drop-Out Voltage Regulators: Capacitor-less Architecture Comparison. IEEE Circuits and Devices Magazine, Vol. 14, no. 2, 2014, pp. 6 – 26. DOI 10.1109/MCAS.2014.2314263

  42. Peesapati R., Sabat S.L., Karthik, K. P., Narasimhappa M., Giribabu N., Nayak J.: FPGA-based embedded platform for fiber optic gyroscope signal denoising. Int. J. of Circuit Theory and Applications, Vol. 42, no. 7, 2014, pp. 744 – 757. DOI 10.1002/cta.1883

  43. Bozorgzadeh B., Covey D.P., Howard C.D., Garris P.A., Mohseni P.: A Neurochemical Pattern Generator SoC With Switched-Electrode Management for Single-Chip Electrical Stimulation and 9.3 mu W, 78 pA(rms), 400 V/s FSCV Sensing. IEEE Journal of SSC, Vol. 49, no. 4, 2014, Special Issue: SI, pp. 881 – 895. DOI 10.1109/JSSC.2014.2299434

  44. Singh Pawan Kumar, Sharma Sanjay: Substrate Coupling of RF CMOS on Lightly Doped Substrate for Nanoscale Mixed-Signal Design. J. of Computational and Theoretical Nanoscience, Vol. 11, no. 4, 2014, pp. 1184 – 1188. DOI 10.1166/jctn.2014.3480

  45. Park Chang-Joon, Onabajo M., Silva-Martinez J.: External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4-4 MHz Range. IEEE Journal of SSC, Vol. 49, no. 2, 2014, pp. 486 – 501. DOI 10.1109/JSSC.2013.2289897

  46. Chen Wei-Ming, Chiueh Herming, Chen Tsan-Jieh, et al.: A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control. IEEE Journal of SSC, Vol. 49, no. 1 Special Issue: SI, 2014, pp. 232 – 247. DOI 10.1109/JSSC.2013.2284346

  47. Chang-Hyeon Lee, Kabalican L., Yan Ge, Kwantono H., Unruh G., Chambers M., Fujimori I: A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS. Symp. on VLSI Circuits (Digest & Technical Papers), 2014, pp.1 - 2 DOI 10.1109/VLSIC.2014.6858390

  48. Mereni L., Pepe D., Zito D.: Analyses and design of 95-GHz SoC CMOS radiometers for passive body imaging. Analog Integrated Circuits & Signal Processing, Vol. 77, no. 3 Special Issue: SI, 2013, pp. 373 – 383. DOI 10.1007/s10470-013-0194-8

  49. Abdelhalim K., Kokarovtseva L., Velazquez J.L.Perez, Genov R.: 915-MHz FSK/OOK Wireless Neural Recording SoC With 64 Mixed-Signal FIR Filters. IEEE Journal of SSC, Vol. 48, no. 10, 2013, pp. 2478 – 2493. DOI 10.1109/JSSC.2013.2272849

  50. Aminzadeh H.: MOSFET-only Two-Stage Operational Amplifiers with Miller Compensation: Design and Fabrication in Nano-Scale CMOS. J. of Circuits Systems & Computers, Vol. 22, no. 8, 2013, Article # 1350065. DOI 10.1142/S0218126613500655

  51. Peesapati R., Sabat S.L., Anumandla K.K., Kandyala P.K., Nayak J.: Design and implementation of a realtime co-processor for denoising Fiber Optic Gyroscope signal. Digital Signal Processing, Vol. 23, no. 5, 2013, pp. 1813 – 1825. DOI 10.1016/j.dsp.2013.04.010

  52. Seguin-Moreau N.: Latest generation of ASICs for photodetector readout. Nuclear Instruments & Methods in Physics Research: Section A - Accelerators Spectrometers Detectors and Associated Equipment, Vol. 718, 2013, pp. 173 – 179. DOI 10.1016/j.nima.2012.11.134

  53. Lai Xin-Quan, Xing Zhi-Qiang, Shi Ling-Feng, Liu Chen, Du Han-Xiao: Study of Signal Integrity for a Novel Stacked Cylindrical PoP Package. IEEE Int. Symp. on Advanced Packaging Materials (APM), Book Series: Int. Symp. on Advanced Packaging Materials-Processes, Properties & Interfaces, 2013. DOI 10.1109/ISAPM.2013.6510385

  54. Chew W.C., Cangellaris A.C., Schutt-Aine J., Braunisch H., Qian Z.G., Aydiner A.A, Aygun K., Jiang L.J., Ma Z.H., Meng L.L., Naeem M.: Fast and accurate multiscale electromagnetic modeling framework: An overview. IEEE 17th Workshop on Signal and Power Integrity (SPI), 2013 pp.1 – 4. DOI 10.1109/SaPIW.2013.6558315

  55. Savidis I., Kose S., Friedman E.G.: Power Noise in TSV-Based 3-D Integrated Circuits. IEEE Journal of SSC, Vol. 48, no. 2, 2013, pp 587 – 597. DOI 10.1109/JSSC.2012.2217891

  56. Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang: Embedding Repeaters in Silicon IPs for Cross-IP Interconnections. IEEE Trans on VLSI, Vol. 21, no. 3, 2013, pp. 597 – 601. DOI 10.1109/TVLSI.2012.2190434

  57. Takeuchi K., Shimada M., Sato T., Katsuki Y., Yoshikawa H., Matsushita H.: Spatial Distribution Measurement of Dynamic Voltage Drop Caused by Pulse and Periodic Injection of Spot Noise. IEEE Trans on VLSI, Vol. 21, no. 1, 2013, pp. 164 – 168. DOI 10.1109/TVLSI.2011.2180742

  58. Kyoungchoul Koo, Myunghoi Kim, Kim, J.J., Joungho Kim, Jiseong Kim: Vertical Noise Coupling From On-Chip Switching-Mode Power Supply in a Mixed-Signal Stacked 3-D-IC. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 3, no. 3, 2013, pp. 476 – 488. DOI 10.1109/TCPMT.2012.2219621

  59. Saniie J., Oruklu E., Yoon Sungjoon: System-on-Chip Design for Ultrasonic Target Detection Using Split-Spectrum Processing and Neural Networks. IEEE Trans on Ultrasonics, Ferroelectrics and Frequency Control, Vol. 59, no. 7 Special Issue: SI, 2012, pp. 1354 – 1368. DOI 10.1109/TUFFC.2012.2336

  60. Uemura S., Hiraoka Y., Kai T., Dosho S.: Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs. IEEE J. of SSC, Vol. 47, no. 4, 2012, pp. 810 – 816. DOI 10.1109/JSSC.2012.2185169

  61. S. Revathi, R.Radhika : Signal Integrity modeling for high-speed DDRx Using Chip-Package Board analysis. Int. Journal of Power Control Signal and Computation (IJPCSC), Vol. 3, no 1, 2012 ISSN: 0976-268X www.ijcns.com

  62. Oikawa R., Gope D., Jandhyala V.: Return-Path Extraction Technique for SSO Analysis of Low-Cost Wire-Bonding BGA Packages. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 2, no. 4, 2012, pp. 677 – 686. DOI 10.1109/TCPMT.2012.2187015

  63. Myunghoi Kim, Kyoungchoul Koo, Chulsoon Hwang, Yujeong Shim, Joungho Kim, Jonghoon Kim: A Compact and Wideband Electromagnetic Bandgap Structure Using a Defected Ground Structure for Power/Ground Noise Suppression in Multilayer Packages and PCBs. IEEE Trans on EMC, Vol. 54, no. 3, 2012, pp. 689 – 695. DOI 10.1109/TEMC.2012.2187662

  64. Hung-Chuan Chen, Chung-Hao Tsai, Tzong-Lin Wu: A Compact and Embedded Balanced Bandpass Filter With Wideband Common-Mode Suppression on Wireless SiP. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 2, no. 6, 2012, pp.1030 – 1038. DOI 10.1109/TCPMT.2012.2186451

  65. Takatani H., Tanaka Y., Oizono Y., Nabeshima Y., Okumura T., Sudo T., Sakai A., Uchiyama S., Ikeda H.: PDN impedance and noise simulation of 3D SiP with a widebus structure. IEEE 62nd Electronic Components and Technology Conf. (ECTC), 2012, pp. 673 – 677. DOI 10.1109/ECTC.2012.6248904

  66. Hung-Chuan Chen, Chung-Hao Tsai, Tzong-Lin Wu: A Compact and Embedded Balanced Bandpass Filter With Wideband Common-Mode Suppression on Wireless SiP. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 2, no. 6, 2012, pp. 1030 – 1038. DOI 10.1109/TCPMT.2012.2186451

  67. Alimenti F., Mezzanotte P., Tasselli G., Battistini A., Palazzari V., Roselli L.: Development of Low-Cost 24-GHz Circuits Exploiting System-in-Package (SiP) Approach and Commercial PCB Technology. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 2, no. 8, 2012, pp.1265 – 1274. DOI 10.1109/TCPMT.2012.2184111

  68. Stamatiadis C., Kalavrouziotis D., Pagano A., Morro R., Riccardi E., Stampoulidis L., Voigt K., Preve G.B., Moerl L., Kreissl J., Landles K., Duffy S., Avramopoulos H., Zimmermann L., Petermann K.: Photonic Provisioning Using a Packaged SOI Hybrid All-Optical Wavelength Converter in a Meshed Optical Network Testbed. Journal of Lightwave Technology, Vol. 30, no 18, 2012, pp. 2941 – 2947. DOI 10.1109/JLT.2012.2209172

  69. Sanming Hu, Yong-Zhong Xiong, Lei Wang, Rui Li, Jinglin Shi, Teck-Guan Lim: Compact High-Gain mmWave Antenna for TSV-Based System-in-Package Application. IEEE Trans on Components, Packaging and Manufacturing Technology, Vol. 2, no 5, 2012, pp. 841 – 846. DOI 10.1109/TCPMT.2012.2188293

  70. Raj P.M., Sharma H., Mishra D., Murali K.P., Kyuhwan Han, Swaminathan, M., Tummala, R.R.: Nanomagnetics for High-Performance, Miniaturized Power, and RF Components [Nanopackaging]. IEEE Nanotechnology Magazine, Vol. 6, no 3, 2012, pp. 18 – 23. DOI 10.1109/MNANO.2012.2203878

  71. Xuequan Yu, Yadong Bai, Yan Zhou, Wei Bai, Lin Yang, Junxin Min: EMI study of high-speed IC package based on pin map. Asia-Pacific Symp. on Electromagnetic Compatibility (APEMC), 2012, pp. 305 – 308. DOI 10.1109/APEMC.2012.6237855

  72. Oizono Yoshiaki, Nabeshima Yoshitaka, Okumura Takafumi, Sudo Toshio, Sakai Atsushi, Uchiyama Shiro, Ikeda Hiroaki: PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structure. IEEE Int. 3D Systems Integration Conference (3DIC), 2012, pp. 1 – 2. DOI 10.1109/3DIC.2012.6263028

  73. Matsushima T., Asai R., Nishimoto T., Wada O.: Degradation of signal integrity due to package-common-mode resonance caused by external conductive noise in power supply system. Asia-Pacific Symp. on Electromagnetic Compatibility (APEMC), 2012, pp. 85 – 88. DOI 10.1109/APEMC.2012.6237999

  74. Benfica J., Bolzani Poehls L., Vargas F., Lipovetzky J., Lutenberg A., Garcia S.E.: Configurable platform for SoC combined tests of TID radiation, aging and EMI. Asia-Pacific Symp. on Electromagnetic Compatibility (APEMC), 2012, pp. 393 – 396. DOI 10.1109/APEMC.2012.6237989

  75. Zhenxian Liang, Puqi Ning, Wang F., Marlino L.: Reducing Parasitic Electrical Parameters with a Planar Interconnection Packaging Structure. 7th Int. Conf on Integrated Power Electronics Systems (CIPS), 2012, pp. 1 – 6. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6170650&isnumber=6170617

  76. Lee J.K., Stoffel N., Fite K.: Electronic packaging of sensors for lower limb prosthetics. IEEE 62nd Electronic Components and Technology Conf (ECTC), 2012, pp. 86 – 91. DOI 10.1109/ECTC.2012.6248811

  77. Chinq-Shiun Chiu, Hsiang-Hui Chang, Tzung-Han Wu, Shin-Fu Chen, Chieh-Chuan Chin, Wei-Kai Hong, Sheng Jau Wong, Li-Shin Lai, Chi-Hsueh Wang, Song-Yu Yang, Ta-Hsin Lin, Jhy-Rong Chen, Hung-Chieh Tsai, Hsi-Ming Yang, Hsiao-Wei Chen, Marques A., Caiyi Wang, Chien G.: A 65nm GSM/GPRS/EDGE SoC with Integrated BT/FM. IEEE Radio Frequency Integrated Circuits Symp. (RFIC), 2012, pp. 403 – 406. DOI 10.1109/RFIC.2012.6242309

  78. Chandrashekar K., Pellerano S., Madoglio P., Ravi A., Palaskas Y.: A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management. IEEE Int. Solid-State Circ. Conf. Digest of Technical Papers (ISSCC), 2012, pp. 352 – 354. DOI 10.1109/ISSCC.2012.6177048

  79. Yuan Liang: RF NMOS switch, front end, up converted mixer, LC-VCO co-design in a SoC-based sensor chip in 0.13μm CMOS. Int. Conf. on System Science and Engineering (ICSSE), 2012, pp. 389 – 394. DOI 10.1109/ICSSE.2012.6257214

  80. Minchul Shin, Myunghoi Kim, Kyoungchoul Koo, Sunkyu Kong, Joungho Kim : Design and experimental verification of on-chip signal integrity analyzer (OSIA) scheme for eye diagram monitoring of a high-speed serial link. IEEE Int. Symp. on Electromagnetic Compatibility (EMC), 2011, pp. 119 – 125. DOI 10.1109/ISEMC.2011.6038295

  81. Wu Boping, Mo Tingting : Printed circuit board electrical design for wafer-level packaging. 12th Int. Conf. on Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2011, pp. 1 – 4. DOI 10.1109/ICEPT.2011.6066808

  82. Kyoungchoul Koo, Myunghoi Kim, Sangrok Lee, Joungho Kim : Measurement and analysis of vertical noise coupling on low noise amplifier from on-chip switching-mode DC-DC converter in 3D-IC. IEEE Int. Symp. on Electromagnetic Compatibility (EMC), 2011, pp. 22 – 27. DOI 10.1109/ISEMC.2011.6038278

  83. Bumhee Bae, Yujeong Shim, Jonghyun Cho, Joungho Kim : Simultaneous switching noise coupling through via transition for a CMOS negative feedback Operational Amplifier in System-in-Package. IEEE 54th Int. Midwest Symp. on Circuits and Systems (MWSCAS), 2011, pp 1 – 4. DOI 10.1109/MWSCAS.2011.6026494

  84. Sasaki H., Tsukuda T., Fujimura Y., Murakami T., Terai H. : Investigation of noise coupling in mixed-signal system-in-packages (SiPs). 8th Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo), 2011, pp.194 – 197.

  85. Bencivinni M., Camarda F., Capriglione D., Chiariello A.G., Fusillo G., Girardi A., Izzi R., Maffucci A., Martines I.: Characterization and modeling of the electromagnetic behavior of ICs and packages. Int. Conf. on Electromagnetics in Advanced Applications (ICEAA), 2011, pp. 1368 – 1371. DOI 10.1109/ICEAA.2011.6046276

  86. Mohajer-Iravani B., Ramahi O.M.: Reactive power radiated from the planar electromagnetic bandgap structures, a source of EMI in high speed packages. IEEE Int. Symp. on Antennas and Propagation (APSURSI), 2011, pp. 1840 – 1843. DOI 10.1109/APS.2011.5996855

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