Home
Glossary
Acronyms
Beware
Contact
 
 

NOISE in LOGIC CIRCUITS and SYSTEMS

Grau, teurer Freund, ist alle Theorie,

Und grün des Lebens goldner Baum”

(W. Goethe)

  1. Kang Yoonhwan, Bokor Jeffrey, Stojanovic V.: Design Requirements for a Spintronic MTJ Logic Device for Pipelined Logic Applications. IEEE Trans on ED, Vol. 63, no. 4, 2016, pp. 1754 – 1761. DOI 10.1109/TED.2016.2527046

  2. Bhowmik Suman, Deb Debajit, Pradhan Sambhu Nath, et al.: Reduction of Noise Using Continuously Changing Variable Clock and Clock Gating for IC Chips. IEEE Trans on Components, Packaging & Manufacturing Technology, Vol. 6, no. 6, 2016, pp. 886 – 896. DOI 10.1109/TCPMT.2016.2562143

  3. Trivedi R., Khankhoje U.K., Majumdar A.: Cavity-Enhanced Second-Order Nonlinear Photonic Logic Circuits. Physical Review Applied, Vol. 5, no. 5, 2016, Article # 054001. DOI 10.1103/PhysRevApplied.5.054001

  4. Kwon Jimin, Kyung Sujeong, Yoon Sejung, et al.: Solution-Processed Vertically Stacked Complementary Organic Circuits with Inkjet-Printed Routing. Advanced Science, Vol. 3, no. 5, 2016, Article # 1500439. DOI 10.1002/advs.201500439

  5. Thakur Chetan Singh, Afshar Saeed, Wang Runchun M., et al.: Bayesian Estimation and Inference Using Stochastic Electronics. Frontiers in Neuroscience, Vol. 10, 2016, Article # 104. DOI 10.3389/fnins.2016.00104

  6. Zeidler S., Fan Xin, Schrape O., et al.: An Early Stage Design Flow for Switching Noise Attenuation. J. of Circuits, Systems & Computers, Vol. 25, no. 3, 2016, Article # 1640022. DOI 10.1142/S0218126616400223

  7. Sui Chunchun, Ren Liehui, Gao Xu, et al.: Predicting Statistical Characteristics of Jitter Due to Simultaneous Switching Noise. IEEE Trans on EMC, Vol. 58, no. 1, 2016, pp. 249 – 256. DOI 10.1109/TEMC.2015.2474124

  8. Zhao Yudan, Li Qunqing, Xiao Xiaoyang, et al.: Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks. ACS Nano, Vol. 10, no. 2, 2016, pp. 2193 – 2202. DOI 10.1021/acsnano.5b06726

  9. Puglisi F.M., Deleruyelle D., Portal J.M., et al.: A multi-scale methodology connecting device physics to compact models and circuit applications for OxRAM technology. Physica Status Solidi A - Applications & Materials Science, Vol. 213, no. 2, 2016, pp. 289 – 301. DOI 10.1002/pssa.201532828

  10. Zhao Qinghang, Liu Yongpan, Zhao Jiaqing, et al.: Noise Margin Modeling for Zero-V-GS Load TFT Circuits and Yield Estimation. IEEE Trans on ED, Vol. 63, no. 2, 2016, pp. 684 – 690. DOI 10.1109/TED.2015.2506722

  11. Manipatruni Sasikanth, Nikonov D.E., Young I.A.: Material Targets for Scaling All-Spin Logic. Physical Review Applied, Vol. 5, no. 1, 2016, Article # 014002. DOI 10.1103/PhysRevApplied.5.014002

  12. Shin J., Kim W., Ngo K.D.T.: DBC Switch Module for Management of Temperature and Noise in 220-W/in3 Power Assembly. IEEE Trans on Power Electronics, Vol. 31, no. 3, 2016, pp. 2387 – 2394. DOI 10.1109/TPEL.2015.2441119

  13. Kim K., Kim S.: Design of Schmitt Trigger Logic Gates Using DTMOS for Enhanced Electromagnetic Immunity of Subthreshold Circuits. IEEE Trans on EMC, Vol. 57, no. 5, 2015, pp. 963 – 972. DOI 10.1109/TEMC.2015.2427992

  14. Soni Sheetal, Akashe Shyam: Enhanced Power Gating Schemes for Low Leakage Power and Low Ground Bounce Noise in Design of Ring Oscillator. Wireless Personal Communications, Vol. 80, no. 4, 2015, pp. 1517 – 1533. DOI 10.1007/s11277-014-2096-1

  15. Bednarz C., Beyer J., Leone M.: Broadband Switching Noise Estimation of Resonant Low-Loss Structures for Unipolar Pulse Excitation. IEEE Trans on EMC, Vol. 57, no. 3, 2015, pp. 599 – 602. DOI 10.1109/TEMC.2015.2407414

  16. Yiting Jia, Donglai Zhang, Bin Zhang: Slit-Surface Disturbance Lattice EBG Structure for Simultaneously Switching Noise Suppression in High-Speed Data Acquisition System. IEEE Trans on Components, Packaging & Manufacturing Technology, Vol. 5, no. 1, 2015, pp. 86 – 98. DOI 10.1109/TCPMT.2014.2376875

  17. Huanyu He, Lu, J.J.-Q.: Modeling and Analysis of PDN Impedance and Switching Noise in TSV-Based 3-D Integration. IEEE Trans on ED, Vol. 62, no. 4, 2015, pp. 1241 – 1247. DOI 10.1109/TED.2015.2396914

  18. Xiaonan Yang, Zhiwei Zheng, Yan Wang, Zongliang Huo, Lei Jin, Dandan Jiang, Zhongyong Wang, Shengfen Chiu, Hanming Wu, Ming Liu: Gate Bias Dependence of Complex Random Telegraph Noise Behavior in 65-nm NOR Flash Memory. IEEE ED Lett., Vol. 36, no. 1, 2015, pp. 26 – 28. DOI 10.1109/LED.2014.2367104

  19. Gao X., Sui C., Hemmady S., Rivera J., Yakura S.J., Pommerenke D., Patnaik A., Beetner D.G.: Modeling Static Delay Variations in Push–Pull CMOS Digital Logic Circuits Due to Electrical Disturbances in the Power Supply. IEEE Trans on EMC, Vol. 57, no. 5, 2015, pp. 1179 – 1187. DOI 10.1109/TEMC.2015.2428272

  20. Kwon M., Gun Kam D.: Removal of Specific Harmonics by Rise Time Control. IEEE Trans on EMC, Vol. 57, no. 5, 2015, pp. 1274 – 1276. DOI 10.1109/TEMC.2015.2426202

  21. Junyoung Ko, Jisu Kim, Youngdon Choi, Park H.K., Seong-Ook Jung: Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM. IEEE Trans on CAS I : Regular Papers, Vol. 62, no. 8, 2015, pp. 2091 – 2102. DOI 10.1109/TCSI.2015.2452352

  22. Kaplan Y., Wimer S.: Mixing Drivers in Clock-Tree for Power Supply Noise Reduction. IEEE Trans on CAS I : Regular Papers, Vol. 62, no. 5, 2015, pp. 1382 – 1391. DOI 10.1109/TCSI.2015.2411778

  23. Resnati D., Compagnoni C.M., Paolucci G.M., Miccoli C., Spinelli A.S., Lacaita A.L., Visconti A., Goda A.: Random Telegraph Noise-Induced Sensitivity of Data Retention to Cell Position in the Programmed Distribution of NAND Flash Memory Arrays. IEEE ED Lett., Vol. 36, no. 7, 2015, pp. 678 – 680. DOI 10.1109/LED.2015.2428282

  24. Chiang Chien-Hsueh, Li Yiming: Design, Fabrication and Characterization of Low-Noise and High-Reliability Amorphous Silicon Gate Driver Circuit for Advanced FPD Applications. J. of Display Technology, Vol. 11, no. 8, 2015, pp. 633 – 639. DOI 10.1109/JDT.2014.2387880

  25. Blank M., Gluck T., Kugi A., Kreuter H.-P.: Digital Slew Rate and S-Shape Control for Smart Power Switches to Reduce EMI Generation. IEEE Trans on Power Electronics, Vol. 30, no. 9, 2015, pp. 5170 – 5180. DOI 10.1109/TPEL.2014.2361021

  26. Han-Nien Lin, Chung-Wei Kuo, Hung-Chi Chen: Electromagnetic interference noise suppression of writing/reading flash memory with multiple-execution control program. IET Science, Measurement & Technology, Vol. 9, no. 8, 2015, pp. 1032 – 1038. DOI 10.1049/iet-smt.2015.0078

  27. Cortez M., Hamdioui S., Kaichouhi A., van der Leest V., Maes R., Schrijen G.-J.: Intelligent Voltage Ramp-Up Time Adaptation for Temperature Noise Reduction on Memory-Based PUF Systems. IEEE Trans on CAD of Integrated Circuits and Systems, Vol. 34, no. 7, 2015, pp. 1162 – 1175. DOI 10.1109/TCAD.2015.2422844

  28. Liehui Ren, Tun Li, Chandra S., Xiaohe Chen, Bishnoi H., Shishuang Sun, Boyle P., Zamek I., Jun Fan, Beetner D.G., Drewniak J.L.: Prediction of Power Supply Noise From Switching Activity in an FPGA. IEEE Trans on EMC, Vol. 56, no. 3, 2014, pp. 699 – 706. DOI 10.1109/TEMC.2013.2293872

  29. Shih-Hsien Wu, Yo-Shen Lin: A Wideband Noise-Isolation Bandstop Power Distribution Network Using Quarter-Wavelength Line-Based Structure. IEEE Trans on Components, Packaging & Manufacturing Technology, Vol. 4, no. 6, 2014, pp. 1071 – 1081. DOI 10.1109/TCPMT.2014.2308277

  30. Hui-Wen Tsai, Ming-Dou Ker: Active Guard Ring to Improve Latch-Up Immunity. IEEE Trans on ED, Vol. 61, no. 12, 2014, pp. 4145 – 4152. DOI 10.1109/TED.2014.2363171

  31. Jiwu Lu, Jiao G., Vaz C., Campbell J.P., Ryan J.T., Cheung K.P., Bersuker G., Young C.: PBTI-Induced Random Timing Jitter in Circuit-Speed Random Logic. IEEE Trans on ED, Vol. 61, no. 11, 2014, pp. 3613 – 3618. DOI 10.1109/TED.2014.2357675

  32. Ambrogio S., Balatti S., Cubeta A., Calderoni A., Ramaswamy N., Ielmini D.: Statistical Fluctuations in HfOx Resistive-Switching Memory: Part II—Random Telegraph Noise. IEEE Trans on ED, Vol. 61, no. 8, 2014, pp. 2920 – 2927. DOI 10.1109/TED.2014.2330202

  33. Pandey R., Saripalli V., Kulkarni J.P., Narayanan V., Datta S.: Impact of Single Trap Random Telegraph Noise on Heterojunction TFET SRAM Stability. IEEE ED Lett., Vol. 35, no. 3, 2014, pp. 393 – 395. DOI 10.1109/LED.2014.2300193

  34. Saeidi R., Sharifkhani M., Hajsadeghi K.: Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell. IEEE Trans on CAS I : Regular Papers, Vol. 61, no. 12, 2014, pp. 3386 – 3393. DOI 10.1109/TCSI.2014.2327334

  35. Chang N.C.-J., Hurst P.J., Levy B.C., Lewis S.H.: Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors. IEEE Journal of Solid State Circ., Vol. 49, no. 6, 2014, pp. 1397 – 1407. DOI 10.1109/JSSC.2014.2314446

  36. Bongjin Kim, Weichao Xu, Kim C.H.: A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter. IEEE Journal of Solid State Circ., Vol. 49, no. 4, 2014, pp. 1017 – 1026. DOI 10.1109/JSSC.2013.2294323

  37. Fuketa H., Nomura M., Takamiya M., Sakurai T.: Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits. IEEE Journal of Solid State Circ., Vol. 49, no. 2, 2014, pp. 536 – 544. DOI 10.1109/JSSC.2013.2294172

  38. Matsumoto Takashi, Kobayashi Kazutoshi, Onodera Hidetoshi: Impact of Random Telegraph Noise on CMOS Logic Circuit Reliability. 36th IEEE Custom Integrated Circuits Conf (CICC), 2014, pp. 1 – 8. DOI 10.1109/CICC.2014.6945997

  39. R.A. Sporea, M.J. Trainor, N.D. Young, J.M. Shannon, S.R.P. Silva: Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits. Scientific Reports, Vol. 4, 2014, Article # 4295. DOI 10.1038/srep04295

  40. I-Chyn Wey, Chun-Wei Chang, Yu-Cheng Liao, Heng-Jui Chou: Noise-Tolerant Dynamic CMOS Circuits Design by Using True Single-Phase Clock Latching Technique. Int. J. of Circuit Theory and Applications, 2014. DOI 10.1002/cta.1976 http://onlinelibrary.wiley.com/doi/10.1002/cta.1976/abstract

  41. Wey I-Chyn, Shen Ye-Jhih: Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits. Integration, the VLSI Journal, Vol. 47, no. 4, 2014, pp. 431 – 442. DOI 10.1016/j.vlsi.2013.12.003

  42. Fuketa Hiroshi, Takahashi Ryo, Takamiya Makoto, Nomura Masahiro, Shinohara Hirofumi, Sakurai Takayasu: Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits. IEEE J. of SSC, Vol. 48, no. 8, Special Issue: SI, 2013, pp. 19861994. DOI 10.1109/JSSC.2013.2258831

  43. Ramanujan A., Lafon F., Fernandez-Lopez P.: Practical implementation of conducted EMI noise modeling of switching devices time and frequency-domain approaches. Int. Symp. on Electromagnetic Compatibility (EMC EUROPE), 2013, pp. 753 758. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6653400&isnumber=6653179

  44. Tripathi J.N., Mukherjee J., Apte P.R., Nagpal R.K., Chhabra N.K., Malik R.: A novel EBG structure with super-wideband suppression of simultaneous switching noise in high speed circuits. IEEE Conf on Electrical Performance of Electronic Packaging & Systems (EPEPS), 2013, pp. 243 246. DOI 10.1109/EPEPS.2013.6703509

  45. I-Chyn Wey, Yi-Jung Lan, Chien-Chang Peng: Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design. Microelectronics Reliability, Vol. 53, no. 12, 2013, pp. 2057 – 2069. DOI 10.1016/j.microrel.2013.06.002

  46. Mohammad B., Homouz D., Elgabra H.: Robust Hybrid Memristor-CMOS Memory: Modeling and Design. IEEE Trans on VLSI, Vol. 21, no. 11, 2013, pp. 2069 – 2079. DOI 10.1109/TVLSI.2012.2227519

  47. Hamza D., Mei Qiu: Digital Active EMI Control Technique for Switch Mode Power Converters. IEEE Trans on EMC, Vol. 55, no. 1, 2013, pp 81 – 88. DOI 10.1109/TEMC.2012.2213590

  48. Chuen-De Wang, Tzong-Lin Wu: Model and Mechanism of Miniaturized and Stopband-Enhanced Interleaved EBG Structure for Power/Ground Noise Suppression. IEEE Trans on EMC, Vol. 55, no. 1, 2013, pp. 159 – 167. DOI 10.1109/TEMC.2012.2210900

  49. Shih-Yi Yuan, Yu-Lun Wu, Perdriau R., Shry-Sann Liao: Detection of Electromagnetic Interference in Microcontrollers Using the Instability of an Embedded Phase-Lock Loop. IEEE Trans on EMC, Vol. 55, no. 2, 2013, pp. 299 – 306. DOI 10.1109/TEMC.2012.2218285

  50. Moon J., No J., Lee S., Kim S., Choi S., Song Y.: Statistical Characterization of Noise and Interference in NAND Flash Memory. IEEE Trans on CAS I: Regular Papers, Vol. 60, no. 8, 2013, pp 2153 – 2164. DOI 10.1109/TCSI.2013.2239116

  51. Halpern M.E.: Maximum Reduction in Peak Voltage Using Stepped Currents to Deliver Charge to RC Circuits. IEEE Trans on CAS II: Express Briefs, Vol. 60, no. 7, pp 407,411, 2013 DOI 10.1109/TCSII.2013.2258269

  52. Cui Q., Si M., Sporea R.A., Guo X.: Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits. IEEE Trans on ED, Vol. 60, no. 5, 2013, pp. 1782 – 1785. DOI 10.1109/TED.2013.2251346

  53. Delker C.J., Zi Y., Yang C., Janes D.B.: Low-Frequency Noise Contributions From Channel and Contacts in InAs Nanowire Transistors. IEEE Trans on ED, Vol. 60, no. 9, 2013, pp. 2900 – 2905. DOI 10.1109/TED.2013.2274009

  54. Ravezzi L.: Clock buffer with supply noise active compensation for reduced period jitter. Electronics Lett., Vol. 49, no. 18, 2013, pp 1130 – 1131. DOI 10.1049/el.2013.1178

  55. Liang-Shun Chang, Chien-Yuan Huang, Yuan-Heng Tseng, Ya-Chin King, Chrong-Jung Lin: Temperature Sensing Scheme Through Random Telegraph Noise in Contact RRAM. IEEE ED Lett., Vol. 34, no. 1, 2013, pp. 12 – 14. DOI 10.1109/LED.2012.2226137

  56. Chen Zheng, Chowdhury I., Dongsheng Ma: Low-Noise Switched-Capacitor Power Converter With Adaptive On-Chip Surge Suppression and Preemptive Timing Control. IEEE Trans on Power Electronics, Vol. 28, no.11, 2013, pp 5174 – 5182. DOI 10.1109/TPEL.2013.2240015

  57. Todri A., Bosio A., Dilillo L., Girard P., Virazel A.: Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Trans on VLSI, Vol. 21, no. 5, 2013, pp. 958 – 970. DOI 10.1109/TVLSI.2012.2197427

  58. Charania T., Opal A., Sachdev M.: Analysis and Design of On-Chip Decoupling Capacitors. IEEE Trans on VLSI, Vol. 21, no. 4, 2013, pp.648 – 658. DOI 10.1109/TVLSI.2012.2198501

  59. Hailong Jiao, Kursun V.: Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits. IEEE Trans on VLSI, Vol. 21, no. 3, 2013, pp.533 – 545. DOI 10.1109/TVLSI.2012.2190116

  60. Aadithya K.V., Demir A., Venugopalan S., Roychowdhury J.: Accurate Prediction of Random Telegraph Noise Effects in SRAMs and DRAMs. IEEE Trans on CAD of Integrated Circuits and Systems, Vol. 32, no. 1, 2013, pp. 73 – 86. DOI 10.1109/TCAD.2012.2212897

  61. Li Fu-Hai, Shirota Riichiro: Impact of Source/Drain Junction and Cell Shape on Random Telegraph Noise in NAND Flash Memory. Japanese Journal of Applied Physics, Vol. 52, no. 7, 2013, Article # UNSP 074201. DOI 10.7567/JJAP.52.074201

  62. Gune A., Gupta A.: Graphene nanoribbon based static random access memory for better noise margin and power reduction. Int. Conf. on Advanced Nanomaterials and Emerging Eng. Technologies (ICANMEET), 2013, pp. 450 – 452.DOI 10.1109/ICANMEET.2013.6609342

  63. Maccaronio V., Crupi F., Procel L. M., Goux L., Simoen E, Trojman L., Miranda E.: DC and low-frequency noise behavior of the conductive filament in bipolar HfO2-based resistive random access memory. Microelectronic Eng., Vol. 107, 2013, pp. 1 – 5. DOI 10.1016/j.mee.2013.02.076

  64. Jo Bong-Su, Kang Ho-Jung, Joe Sung-Min, Jeong Min-Kyu, Han Kyung-Rok, Park Sung-Kye, Park Byung-Gook, Lee Jong-Ho: Characterization of Random Telegraph Noise Generated by Process- and Cycling-Stress-Induced Traps in 26 nm NAND Flash Memory. Japanese Journal of Applied Physics, Vol. 52, no. 4, Part: 2, 2013, Special no. SI, Article # UNSP 04CA07. DOI 10.7567/JJAP.52.04CA07

  65. Eudes T., Ravelo B.: Analysis of multi-gigabits signal integrity through clock H-tree. Int. J. of Circuit Theory and Applications, Vol. 41, no. 5, 2013, pp. 535 – 549. DOI 10.1002/cta.818

  66. Sawada Takuya, Takata Hidehiro, Nii Koji, Nagata Makoto: False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation. Japanese Journal of Applied Physics, Vol. 52, no. 4, Special no. SI, Part: 2, 2013, Article # UNSP 04CE14. DOI 10.7567/JJAP.52.04CE14

  67. G. Betti Beneventi, M. Ferro, P. Fantini: 1/f noise in 45nm RESET-state Phase-Change Memories: characterization, impact on memory readout operation, and scaling perspectives. IEEE Electron Devices Letters, Vol. 33, no. 11, 2012, pp. 1559 – 1561. DOI 10.1109/LED.2012.2214472

  68. Gili X., Barcelo S., Bota S.A., Segura J.: Analytical Modeling of Single Event Transients Propagation in Combinational Logic Gates. IEEE Trans. on Nuclear Science, Vol. 59, no. 4, Part 1, 2012, pp. 971 – 979. DOI 10.1109/TNS.2012.2187071

  69. Simoen E., de Andrade M. G. C., Aoulaiche M., Collaert N., Claeys C.: Low-Frequency-Noise Investigation of n-Channel Bulk FinFETs Developed for One-Transistor Memory Cells. IEEE Trans. on ED, Vol. 59, no. 5, 2012, pp. 1272 – 1278. DOI 10.1109/TED.2012.2186815

  70. Tsormpatzoglou A., Hastas N. A., Khan S., Hatalis M., Dimitriadis C. A.: Comparative Study of Active-Over-Metal and Metal-Over-Active Amorphous IGZO Thin-Film Transistors With Low-Frequency Noise Measurements. IEEE ED Letters, Vol. 33, no. 4, 2012, pp. 555 – 557. DOI 10.1109/LED.2012.2185677

  71. Mu-Shui Zhang, Hong-Zhou Tan, Jun-Fa Mao: Worst Case Power Noise Estimation and Compensation Design for Zero Coupling with Multiple Switching I/Os. IEEE Trans on EMC, Vol. 54, no. 5, 2012, pp. 1105 – 1111. DOI 10.1109/TEMC.2012.2192444

  72. Bona C., Fiori F.: A New Front-End for Binary Data Recovery in EM Polluted Environment. IEEE Trans on CAS I : Regular Papers, Vol. 59, no. 10, 2012, pp. 2232 – 2243. DOI 10.1109/TCSI.2012.2189039

  73. Bait-Suwailam M.M., Ramahi O.M.: Ultrawideband Mitigation of Simultaneous Switching Noise and EMI Reduction in High-Speed PCBs Using Complementary Split-Ring Resonators. IEEE Trans on EMC, Vol. 54, no. 2, 2012, pp. 389 – 396. DOI 10.1109/TEMC.2011.2163940

  74. Moon Jaekyun, No Jaehyeong, Lee Sangchul, Kim Sangsik, Yang Joongseop, Chang Seung Ho: Noise and interference characterization for MLC flash memories. Int. Conf. on Computing, Networking and Communications (ICNC), 2012, pp. 588 – 592. DOI 10.1109/ICCNC.2012.6167491

  75. Nakagawa Tatsuo, Osada Kenichi: Pulse position/width collaborative control for reducing EMI noise and ripple voltage in switching DC-DC converter. 27th Annual IEEE Applied Power Electronics Conf. and Exposition (APEC), 2012, pp. 1112 – 1116. DOI 10.1109/APEC.2012.6165957

  76. S. Revathi, R.Radhika : Signal Integrity modeling for high-speed DDRx Using Chip-Package Board analysis. Int. Journal of Power Control Signal and Computation (IJPCSC), Vol 3, no 1, 2012 ISSN: 0976-268X www.ijcns.com

  77. Shuto Yusuke, Yamamoto Shuu'ichirou, Sugahara Satoshi: Static Noise Margin and Power-Gating Efficiency of a New Nonvolatile SRAM Cell Based on Pseudo-Spin-Transistor Architecture. 4th IEEE Int. Memory Workshop (IMW), 2012, pp. 1 – 4. DOI 10.1109/IMW.2012.6213624

  78. Jayashree H.V., Harsha K.: Four BIT CMOS full adder in submicron technology with low leakage and Ground bounce noise reduction. Int. Conf on Devices, Circuits and Systems (ICDCS), 2012, pp. 20 – 24. DOI 10.1109/ICDCSyst.2012.6188780

  79. Weng-Yew Chang, Wei-Shan Soh, Kye-Yak See, Lin-Biao Wang: Extraction of Clock Driver Output Impedance for Signal Integrity Design. IEEE Trans on EMC, Vol. 53, no. 4, 2011, pp. 1034 – 1039. DOI 10.1109/TEMC.2011.2162096

  80. Junfeng Zhou, Dehaene W.: An On-Chip Power Supply Regulator to Reduce the Switching Noise. IEEE Trans on EMC, Vol. 53, no. 1, 2011, pp. 157 – 168. DOI 10.1109/TEMC.2010.2052053

  81. Purnima Sharma, Rajeevan Chandel, Sankar Sarkar : Noise Tolerant Techniques in Super and Sub-threshold Regions of TSPC logic. Special no of Int. Journal of Computer Applications (0975 – 8887) on Electronics, Information and Comm.Eng. – ICEICE, no. 5, 2011, pp. 25 – 28. http://research.ijcaonline.org/iceice/number5/iceice039.pdf

  82. Shimeng Yu, Jeyasingh R., Yi Wu, Wong H.-S.P.: Understanding the conduction and switching mechanism of metal oxide RRAM through low frequency noise and AC conductance measurement and analysis. IEEE Int. Electron Devices Meeting (IEDM), 2011, pp.12.1.1 – 12.1.4. DOI 10.1109/IEDM.2011.6131537

  83. Jeyasingh R., Chroboczek J.A., Ghibaudo G., Mouis M., Wong H.-S.P.: Low frequency noise in phase change materials. 21st Int. Conf. on Noise and Fluctuations (ICNF), 2011, pp. 476 – 479. DOI 10.1109/ICNF.2011.5994373

  84. Albert M., Flindt C., Buttiker M.: Noise and counting statistics of a single electron emitter: Theory. 21st Int. Conf. on Noise and Fluctuations (ICNF), 2011, pp. 162 – 167. DOI 10.1109/ICNF.2011.5994289

  85. Sachidananda S., Dean A.: EMI- and Energy-Aware Scheduling of Switching Power Supplies in Hard Real-Time Embedded Systems. 17th IEEE Real-Time and Embedded Technology and Applications Symp. (RTAS), 2011, pp. 123 – 133. DOI 10.1109/RTAS.2011.20

  86. Ghetti A., Amoroso S.M., Mauri A., Compagnoni C.M.: Doping Engineering for Random Telegraph Noise Suppression in Deca-Nanometer Flash Memories. 3rd IEEE Int. Memory Workshop (IMW), 2011, pp. 1 – 4. DOI 10.1109/IMW.2011.5873216

  87. Guan-Zong Wu, Yi-Che Chen, Tzong-Lin Wu : Design and Implementation of a Novel Hybrid Photonic Crystal Power/Ground Layer for Broadband Power Noise Suppression. IEEE Trans. on Advanced Packaging, Vol. 33, no. 1, 2010, pp. 206 – 211. DOI 10.1109/TADVP.2009.2034334

  88. Wei Xing-Chang, Shi Zhi-Guo, Li Er-Ping: A Novel Combined Equivalent Networks Analysis for Power and Ground Planes With Narrow Slots. IEEE Trans on EMC, Vol. 52, no. 4, 2010, pp. 994 – 1000. DOI 10.1109/TEMC.2010.2064320

  89. Arakali A., Gondi S., Hanumolu P.K.: Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops. IEEE Trans on CAS I: Regular Papers, Vol. 57, no. 11, 2010, pp. 2880 – 2889. DOI 10.1109/TCSI.2010.2052507

  90. Gang Feng, Jun Fan: Analysis of Simultaneous Switching Noise Coupling in Multilayer Power/Ground Planes With Segmentation Method and Cavity Model. IEEE Trans on EMC, Vol. 52, no. 3, 2010, pp. 699 – 711. DOI 10.1109/TEMC.2010.2046665

  91. Jun Fan, Xiaoning Ye, Jingook Kim, Archambeault B., Orlandi A.: Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions. IEEE Trans on EMC, Vol. 52, no. 2, 2010, pp. 392 – 400. DOI 10.1109/TEMC.2010.2045381

  92. Pattanaik M., Varaprasad Muddala V. D. L., Khan F. R.: Ground bounce noise reduction of low leakage 1-bit nano-CMOS based full adder cells for mobile applications. 2010 Int Conf on Electronic Devices, Systems and Applications (ICEDSA), 2010, pp. 31 – 36. DOI 10.1109/ICEDSA.2010.5503106

  93. Pattanaik M., Khan F. R., Varaprasad Muddala V.D.L.: Improvement of noise tolerance analysis in deep-submicron low voltage dynamic CMOS logic circuits. 2010 Int. Conf on Electronic Devices, Systems and Applications (ICEDSA), 2010, pp. 48 – 53. DOI 10.1109/ICEDSA.2010.5503105

  94. Izydorczyk J.: Three Steps to the Thermal Noise Death of Moore's Law. IEEE Trans on VLSI Syst., Vol. 18, no. 1, 2010, pp. 161 – 165. DOI 10.1109/TVLSI.2008.2008809

  95. Hao-Hsiang Chuang, Wei-Da Guo, Yu-Hsiang Lin, Hsin-Shu Chen, Yi-Chang Lu, Yung-Shou Cheng, Ming-Zhang Hong, Chun-Huang Yu, Wen-Chang Cheng, Yen-Ping Chou, Chuan-Jen Chang, Ku Joseph, Tzong-Lin Wu, Ruey-Beei Wu: Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Coanalysis. IEEE Trans on EMC, Vol. 52, no. 2, 2010, pp. 381 – 391. DOI 10.1109/TEMC.2010.2043108

  96. Hee-do Kang, Hyun Kim, Sang-Gyu Kim, Jong-Gwan Yook: A Localized Enhanced Power Plane Topology for Wideband Suppression of Simultaneous Switching Noise. IEEE Trans on EMC, Vol. 52, no. 2, 2010, pp. 373 – 380. DOI 10.1109/TEMC.2010.2044415

  97. Yun Ye, Chi-Chao Wang, Yu Cao: Simulation of random telegraph Noise with 2-stage equivalent circuit. 2010 IEEE/ACM Int. Conf on Computer-Aided Design (ICCAD), 2010, pp. 709 – 713. DOI 10.1109/ICCAD.2010.5654254

  98. Arabi K.: Power noise and its impact on production test and validation of SoC devices. 28th VLSI Test Symp. (VTS), 2010, pp. 285 DOI 10.1109/VTS.2010.5469550

  99. G. Betti Beneventi, A. Calderoni, P. Fantini, L. Larcher, P. Pavan: Analytical model for low-frequency noise in amorphous chalcogenide-based phase-change memory devices. Journal of Applied Physics, Vol. 106, no. 5, 2009, pp. 054506.1 – 054506.8. DOI 10.1063/1.3160332

  100. I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen, An-Yeu Wu: Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits. IEEE Trans on CAS I : Regular Papers, Vol. 56, no. 11, 2009, pp. 2411 – 2424. DOI 10.1109/TCSI.2009.2015648

  101. Hee-do Kang, Hyun Kim, Hee-Jo Lee, Jong-Gwan Yook : An enhanced power plane topology using localized spiral resonator for wideband suppression of simultaneous switching noise. IEEE Antennas and Propagation Society Int. Symp. (APSURSI '09), 2009, pp 1 – 4. DOI 10.1109/APS.2009.5171508

  102. H.-Q. Zhao, S. Kasai, Y. Shiratori and T. Hashizume : A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regular nanowire network with hexagonal topology. Nanotechnology, Vol. 20, no. 24, 2009, pp. 245203. DOI 10.1088/0957-4484/20/24/245203

  103. Shim Y., Park J., Kim J., Song E., Yoo J., Pak J., Kim J.: Modeling and Analysis of Simultaneous Switching Noise Coupling for a CMOS Negative-Feedback Operational Amplifier in System-in-Package. IEEE Trans on EMC, Vol. 51, no. 3, 2009, pp. 763 – 773. DOI 10.1109/TEMC.2009.2026637

  104. Woojin Lee, Jaemin Kim, Chunghyun Ryu, Jongbae Park, Jun Chul Kim, Joungho Kim: A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator. IEEE Microwave and Wireless Components Letters, Vol. 19, no. 8, 2009, pp. 512 – 514. DOI 10.1109/LMWC.2009.2024841

  105. Xu X., Zhao J., Feng Y.: Achieving both wideband mitigation of ground bounce noise and good signal integrity by novel period structure. Electronics Lett., Vol. 45, no. 3, 2009, pp. 158 – 159. DOI 10.1049/el:20092305

  106. J. Loeckx, G. E. Gielen: Generic and Accurate Whitebox Behavioral Model for Fast Simulation of Analog Effects in Nanometer CMOS Digital Logic Circuits. IEEE Trans on EMC, Vol. 51, no. 2, 2009, pp. 351 – 357. DOI 10.1109/TEMC.2009.2014072

  107. J. Trinkle, A. Cantoni: Impedance Expressions for Unloaded and Loaded Power Ground Planes. Trans on EMC, Vol. 50, no. 2, 2008, pp. 390 – 398. DOI 10.1109/TEMC.2008.919036

  108. M.-D. Ker, T.-H. Lai: Investigation on Robustness of CMOS Devices Against Cable Discharge Event (CDE) Under Different Layout Parameters in a Deep-Submicrometer CMOS Technology. IEEE Trans on EMC, Vol. 50, no. 4, 2008, pp. 810 – 821. DOI 10.1109/TEMC.2008.2004582

  109. Oh K.-I., Kim L.-S., Park K.-I., Jun Y.-H., Kim K.: Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface. Electronics Lett., Vol. 44, no. 19, 2008, pp. 1121 – 1123. DOI 10.1049/el:20081833

  110. Strak A., Gothenberg A., Tenhunen H.: Power-supply and substrate-noise-induced timing jitter in nonoverlapping clock generation circuits. IEEE Trans on CAS I, Vol. 55, no. 4, 2008, pp. 1041 – 1054. DOI 10.1109/TCSI.2008.916565

  111. Siow Chek Tan, Yee Huan Yew, Hong Shi: Crosstalk and switching noise mechanism study in high density wire-bond FPGA device. 33rd IEEE/CPMT Int. Electronic Manufacturing Technology Symp. (IEMT), 2008, pp. 1 – 7. DOI 10.1109/IEMT.2008.5507823

  112. Ting-Kuang Wang, Tzu-Wei Han, Tzong-Lin Wu: A novel power/ground layer using artificial substrate EBG for simultaneously switching noise suppression. IEEE Trans on MTT, Vol. 56, no. 5, part 1, 2008, pp. 1164 – 1171. DOI 10.1109/TMTT.2008.921642

  113. Salomon M.-E., Izouggaghen B., Khouas A., Savaria Y.: Spur Model for a Fixed-Frequency Signal Subject to Periodic Jitter. IEEE Trans on Instr. & Meas., Vol. 57, no. 10, 2008, pp. 2320 – 2328. DOI 10.1109/TIM.2008.922094

  114. K. Kim, A. A. Iliadis: Critical Upsets of CMOS Inverters in Static Operation Due to High-Power Microwave Interference. IEEE Trans on EMC, Vol. 49, no. 4, 2007, pp. 876 – 885. DOI 10.1109/TEMC.2007.908820

  115. Y. Matsumoto, T. Shimizu, T. Murakami, K. Fujii, A. Sugiura: Impact of Frequency-Modulated Harmonic Noises From PCs on OFDM-Based WLAN Systems. IEEE Trans on EMC, Vol. 49, no. 2, 2007, pp. 455 – 462. DOI 10.1109/TEMC.2007.893328

  116. K. Kim, A. A. Iliadis: Impact of Microwave Interference on Dynamic Operation and Power Dissipation of CMOS Inverters. IEEE Trans on EMC, Vol. 49, no. 2, 2007, pp. 329 – 338. DOI 10.1109/TEMC.2007.893333

  117. Kameyama H., Yahagi Y., Ibe E.: A Quantitative Analysis of Neutron-Induced Multi-Cell Upset in Deep Submicron SRAMs and of the Impact Due to Anomalous Noise. Proc of IEEE Int. 45th Annual Reliability Physics Symp., 2007, pp. 678 – 679. DOI 10.1109/RELPHY.2007.369566

  118. J. Qin, O. M. Ramahi, V. Granatstein: Novel Planar Electromagnetic Bandgap Structures for Mitigation of Switching Noise and EMI Reduction in High-Speed Circuits. IEEE Trans on EMC, Vol. 49, no. 3, 2007, pp. 661 – 669. DOI 10.1109/TEMC.2007.902193

  119. Y. Matsumoto: On the Relation Between the Amplitude Probability Distribution of Noise and Bit Error Probability. IEEE Trans on EMC, Vol. 49, no. 4, 2007, pp. 940 – 941. DOI 10.1109/TEMC.2007.908280

  120. Kato H., Kohori T., Kondoh E., Akitsu T., Kato H.: A Noise-Free and Jitterless Cavity System to Distribute Clocks Over 10 GHz. IEEE Trans on MTT, Vol. 54, no. 11, 2006, pp. 3960 – 3967. DOI 10.1109/TMTT.2006.883658

  121. Jongbae Park, Lu A.C.W., Chua K.M., Wai L.L., Junho Lee, Joungho Kim: Double-Stacked EBG Structure for Wideband Suppression of Simultaneous Switching Noise in LTCC-Based SiP Applications. IEEE Microwave and Wireless Comp. Let., Vol. 16, no. 9, 2006, pp. 481 – 483. DOI 10.1109/LMWC.2006.880719

  122. Jie Qin, Ramahi O.M.: Ultra-Wideband Mitigation of Simultaneous Switching Noise Using Novel Planar Electromagnetic Bandgap Structures. IEEE Microwave and Wireless Components Letters, Vol. 16, no. 9, 2006, pp. 487 – 489. DOI 10.1109/LMWC.2006.880713

  123. T.-L. Wu, S.-T. Chen: An electromagnetic crystal power substrate with efficient suppression of power/ground plane noise on high-speed circuits. IEEE Microwave & Wireless Comp. Let., Vol. 16, no. 7, 2006, pp. 413 – 415 DOI 10.1109/LMWC.2006.877124

  124. Wu T.L., Wang T.K.: Embedded power plane with ultra-wide stop-band for simultaneously switching noise on high-speed circuits. Electronics Lett., Vol. 42, no. 4, 2006, pp. 213 – 214. DOI 10.1049/el:20063498

  125. M.-D. Ker, S.-Fu Hsu: Evaluation on Board-Level Noise Filter Networks to Suppress Transient-Induced Latchup in CMOS ICs Under System-Level ESD Test. IEEE Trans on EMC, Vol. 48, no. 1, 2006, pp. 161 – 171. DOI 10.1109/TEMC.2006.870681

  126. J. Meng, W. Ma, Q. Pan, L. Zhang, Z. Zhao: Multiple Slope Switching Waveform Approximation to Improve Conducted EMI Spectral Analysis of Power Converters. IEEE Trans on EMC, Vol. 48, no. 4, 2006, pp. 742 – 751. DOI 10.1109/TEMC.2006.882859

  127. Chien-Lin Wang, Guang-Hwa Shiue, Wei-Da Guo, Ruey-Beei Wu: A Systematic Design to Suppress Wideband Ground Bounce Noise in High-Speed Circuits by Electromagnetic-Bandgap-Enhanced Split Powers. IEEE Trans on MTT, Vol. 54, no. 12, 2006, pp. 4209 – 4217. DOI 10.1109/TMTT.2006.886387

  128. Wiklundh Kia: Relation Between the Amplitude Probability Distribution of an Interfering Signal and its Impact on Digital Radio Receivers. IEEE Trans on EMC, Vol. 48, no. 3, 2006, pp. 537 – 544. DOI 10.1109/TEMC.2006.877782

  129. Y. Matsumoto, K. Fujii, A. Sugiura: Estimating the Amplitude Reduction of Clock Harmonics Due to Frequency Modulation. IEEE Trans on EMC, Vol. 48, no. 4, 2006, pp. 734 – 741. DOI 10.1109/TEMC.2006.884451

  130. M. Camp, H. Garbe: Susceptibility of Personal Computer Systems to Fast Transient Electromagnetic Pulses. IEEE Trans on EMC, Vol. 48, no. 4, 2006, pp. 829 – 833. DOI 10.1109/TEMC.2006.882844

  131. Hoi Lee, Mok P.K.T.: Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler. IEEE J of SSC, Vol. 40, no. 5, 2005, pp. 1136 – 1146. DOI 10.1109/JSSC.2005.845978

  132. Jinseong Choi, Swaminathan M., Nhon Do, Master R.: Modeling of power supply noise in large chips using the circuit-based finite-difference time-domain method. IEEE Trans on EMC, Vol. 47, no. 3, 2005, pp. 424 – 439. DOI 10.1109/TEMC.2005.851719

  133. Kamgaing T., Ramahi O.M.: Design and modeling of high-impedance electromagnetic surfaces for switching noise suppression in power planes. IEEE Trans on EMC, Vol. 47, no. 3, 2005, pp. 479 – 489. DOI 10.1109/TEMC.2005.850692

  134. Shahparnia S., Ramahi O.M.: Miniaturised electromagnetic bandgap structures for broadband switching noise suppression in PCBs. Electronics Lett., Vol. 41, no. 9, 2005, pp. 519 – 520. DOI 10.1049/el:20050445

  135. Nagata M., Okumoto T., Taki K.: A Built-in Technique for Probing Power Supply and Ground Noise Distribution Within Large-Scale Digital Integrated Circuits. IEEE JSSC, Vol. 40, no. 4, 2005, pp. 813 – 819. DOI 10.1109/JSSC.2005.845559

  136. Albuquerque E. F. M., Silva M. M.: A Comparison by Simulation and by Measurement of the Substrate Noise Generated by CMOS, CSL, and CBL Digital Circuits. IEEE Trans on CAS I, Vol. 52, no. 4, 2005, pp. 734 – 741. DOI 10.1109/TCSI.2005.844110

  137. Ding Li, Mazumder Pinaki: Noise-Tolerant Quantum MOS Circuits Using Resonant Tunneling Devices. IEEE Trans on Nanotechnology, Vol. 3, no. 1, 2004, pp. 134 – 146. DOI 10.1109/TNANO.2003.820787

  138. Li Ding, Mazumder P.: Dynamic noise margin: definitions and model. Proc of 17th Int. Conf on VLSI Design, 2004, pp. 1001 – 1006. DOI 10.1109/ICVD.2004.1261061

  139. Wu T.-L., Chen S.-T., Hwang J.-N., Lin Y.-H.: Numerical and Experimental Investigation of Radiation Caused by the Switching Noise on the Partitioned DC Reference Planes of High Speed Interconnects. IEEE Trans on EMC, Vol. 46, no. 1, 2004, pp. 33 – 44. DOI 10.1109/TEMC.2004.823680

  140. Badaroglu M., Van der Plaas G., Wambacq P., Balasubramanian L., Tiri K., Verbauwhede I., Donnay S., Gielen G., De Man H. J.: Digital Circuit Capacitance and Switching Analysis for Ground Bounce in ICs With a high-Ohmic Substrate. IEEE Journal of SSC, Vol. 39, no. 7, 2004, pp. 1119 – 1129. DOI 10.1109/JSSC.2004.829393

  141. Tsukada T., Hashimoto Y., Sakata K., Okada H., Ishibashi K.: An On-Chip Active Decoupling Circuit to Suppress Crosstalk in Deep-Submicron CMOS Mixed-Signal SoCs. IEEE Journal of SSC, Vol. 40, no 1, 2004, pp. 67 – 79. DOI 10.1109/JSSC.2004.838010

  142. Su H., Gala K.H., Sapatnekar S.S.: Analysis and Optimization of Structured Power/Ground Networks. IEEE Trans on CAD, Vol. 22, no. 11, 2003, pp. 1533 – 1544. DOI 10.1109/TCAD.2003.818372

  143. Pamunuwa D., Elassaad S., Tenhunen H.: Modelling noise and delay in VLSI circuits. Electronics Lett., Vol. 39, no. 3, 2003, pp. 269 – 271. DOI 10.1049/el:20030208

  144. Sim S.-P., Krishnan S., Petranovic D.M., Arora N., Lee K., Yang C.Y.: A Unified RLC Model for High-Speed On-Chip Interconnects. IEEE Trans on ED, Vol. 50, no. 6, 2003, pp. 1501 – 1509. DOI 10.1109/TED.2003.813345

  145. Jing-Jia Liou, Krstic A., Yi-Ming Jiang, Kwang-Ting Cheng: Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. IEEE Trans on CAD of Integrated Circuits and Systems, Vol. 22, no. 6, 2003, pp. 756 – 769. DOI 10.1109/TCAD.2003.811442

  146. Tritthart T.: Reducing EMI with Low-EMI Clock Oscillators. http://www.ce-mag.com/archive/03/09/tritthart.htm

  147. Yeap T. H., Fenton D. K., Lefebvre P. D.: A Novel Common-Mode Noise Cancellation Technique for VDSL Applications. IEEE Trans on Instr & Meas, Vol. 52, no 4, 2003, pp. 1325 – 1334. DOI 10.1109/TIM.2003.816850

  148. Kleveland B., Qi X., Maddem L.,Furusawa T., Dutton R., Horrowitz M, Wong S.S.: High-Frequency Characterization of On-Chip Digital Interconnects. IEEE Journal of SSC, Vol. 37, no. 6, 2002, pp. 716 – 724. DOI 10.1109/JSSC.2002.1004576

  149. Mehta J., Bravo D., O K.K.: Switching noise picked up by a planar dipole antenna mounted near integrated circuits. IEEE Trans on EMC, Vol. 44, no. 2, 2002, pp. 282 – 290. DOI 10.1109/TEMC.2002.1003393

  150. Aragones X., Gonzalez J.L., Moll F., Rubio A.: Noise generation and coupling mechanisms in deep-submicron ICs. IEEE Design & Test of Computers, Vol. 19, no. 5, 2002, pp. 27 – 35. DOI 10.1109/MDT.2002.1033789

  151. Bashirullah R., Liu W.: Raised cosine approximation signalling technique for reduced simultaneous switching noise. Electronics Lett., Vol. 38, no. 21, 2002, pp. 1256 – 1258. DOI 10.1049/el:20020852

  152. Zhao S., Roy K., Koh C-K.: Decoupling Capacitance Allocation and its Application to Power-Supply Noise-Aware Floorplanning. IEEE Trans on CAD of Integrated Circuits and Systems, Vol. 21, no. 1, 2002, pp. 81 – 92. DOI 10.1109/43.974140

  153. Ricchiuti V.: Power-Supply Decoupling on Fully Populated High-Speed Digital PCBs. IEEE Trans on EMC, Vol. 43, no. 4, 2001, pp. 671 – 676. DOI 10.1109/15.974649

  154. Madou A., Martens L.: Electrical Behavior of Decoupling Capacitors Embedded in Multilayered PCBs. IEEE Trans on EMC, Vol. 43, no.4, 2001, pp. 549 – 556. DOI 10.1109/15.974634

  155. Kalb J. C.: Nonlinear Termination Techniques for Electronic Systems. http://www.ce-mag.com/archive/01/07/kalb.html

  156. Bertocco M., Narduzzi C., Paglierani P., Petri D.: A Noise Model for Digitized Data. IEEE Trans on Instr. & Meas., Vol. 49, no. 1, 2000, pp. 83 – 86. DOI 10.1109/19.836314

  157. Heijningen M., Compiet J, Wambacq P, Donnay S., Engels M., Bolsens I.: Analysis and Experimental Verification of Digital Substrate Noise Generation for Epi-Type Substrates. IEEE JSSC, Vol. 35, no. 7, July 2000, pp 1002 – 1008. DOI 10.1109/4.848209

  158. Rammuthu I., Emerson P.M., Maggio K., Jiang H., Manjekar A., Bloodworth B.E. Guastaferro M. : A Design for High Noise Rejection in a Pseudo-differential Amplifier for Hard Disk Drives. IEEE Journal of SSC, Vol. 35, no. 6, 2000, pp. 911 – 914. DOI 10.1109/4.845195

  159. Hapanowicz R.: PTC Overcurrent Protection for Universal Serial Bus Circuit Designs. http://www.ce-mag.com/archive/2000/mayjune/hapan.html

  160. Mu F., Svenson C.: Analysis and Optimization of a Uniform Long Wire and Driver. IEEE Trans on Circ & Syst, I, Vol. 46, no. 9, 1999, pp. 1086 – 1100. DOI 10.1109/81.788810

  161. Alpert C., Devgan A., Quay S.: Buffer Insertion for Noise and Delay Optimization. IEEE Trans on CAD of Integr. Circ & Syst., Vol. 18, no. 11, 1999, pp. 1633 – 1644. DOI 10.1109/43.806808

  162. Shepard K.L., Narayanan V., Rose R.: Harmony: static noise analysis of deep submicron digital integrated circuits. IEEE Trans on CAD of Integrated Circuits & Systems, Vol. 18, no. 8, 1999, pp. 1132 – 1150. DOI 10.1109/43.775633

  163. Yi-Min Jiang, Kwang-Ting Cheng: Analysis of performance impact caused by power supply noise in deep submicron devices. Proc of 36th Design Automation Conf., 1999, pp. 760 – 765. DOI 10.1109/DAC.1999.782118

  164. Remley A.K., Weisshaar A., Goodnick S.M., Tripathi V.K.: Characterization of Near- and Far Field Radiation from Ultrafast Electronic Systems. Trans. on MTT, Vol. 46, no.12, 1998, pp. 2476 – 2482. DOI 10.1109/22.739237

  165. H. H. Chen, D. D. Ling: Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design. Proc of 34th DAC, 1997, http://domino.research.ibm.com/comm/research_people.nsf/pages/dling.index.html/$FILE/dling.chen.dac97.pdf

  166. Yang Y., Brews J R.: Crosstalk Estimation for CMOS-Terminated RLC Interconnections. IEEE Trans on CAS I, Vol. 44, no 1, 1997, pp. 82 – 85. DOI 10.1109/81.558447

  167. Shouhong Zhu: A new time-domain model of precise-clock noise. Proc of the 1997 IEEE Int. Frequency Control Symp., 1997, pp. 496 – 501. DOI 10.1109/FREQ.1997.638649

  168. Chappel J. F., Zaky S. G.: EMI Effects and Timing Design for Increased Reliability in Digital Systems. IEEE Trans on CAS I, Vol. 44, no. 2, 1997, pp. 130 – 142. DOI 10.1109/81.554331

  169. Zhu K., Wong D.F.: Clock Skew Minimization During FPGA Placement. IEEE Trans CAD, Vol. 16, no. 4, 1997, pp. 376 – 385. DOI 10.1109/43.602474

  170. Rainal A. J.: Computing inductive noise of CMOS drivers. IEEE Trans on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, Vol. 19, no. 4, 1996, pp. 789 – 802. DOI 10.1109/96.544371

  171. Zhang X.: Coupling Effects on Wire Delay. IEEE Circ.& Devices Mag., 1996, pp. 12 – 18. DOI 10.1109/101.544446

  172. Fried R.: Termination Circuits for Reducing Reflection and Crosstalk. IEEE Trans on CAS I, Vol. 42, no. 12, 1995, pp. 1017 – 1020. DOI 10.1109/81.481197

  173. Furia B.: Capacitor Modeling at High Frequencies – A Pedagogical Example of the Application of Distributed Circuit Analysis for Introductory Electromagnetics or Microwave Courses. IEEE Trans on Education, Vol. 35, no. 3, 1992, pp. 214 – 216. DOI 10.1109/13.144646

  174. Prince J.L., Senthinathan R.: Simultaneous Switching Ground Noise Calculation for Packaged CMOS Devices. IEEE J of SCC, Vol. 26, no 11, Nov 1991, pp 1724 – 1728. DOI 10.1109/4.98995

  175. Wada T., Eino M., Anami K.: Simple Noise Model and Low-Noise Data Output Buffer for Ultrahigh-Speed Memories. IEEE Journal of Solid State Circ., Vol. 25, no. 6, 1990, pp. 1586 – 1588. DOI 10.1109/4.62195

  176. Fairchild Semiconductor: Understanding and Minimizing Ground Bounce. AN-640, June 1989. http://www.fairchildsemi.com/an/AN/AN-640.pdf

  177. National Semiconductors: Digital Noise Reduction Techniques for COMBO II. Applic. Brief TB-02, Oct. 1988.

  178. Katopis G. A.: Delta-I Noise Specification for a High-Performance Computing Machine. Proc. of IEEE, Vol. 73, no. 9, 1985, pp. 1405 – 1415. DOI 10.1109/PROC.1985.13301 and DOI 10.1109/PROC.1985.13382

  179. Lu N.C.C., Chao H.H., Hwang W.: Plate-noise analysis of an on-chip generated half-VDD biased-plate PMOS cell in CMOS DRAMs. IEEE JSSC, Vol. 20, no. 6, 1985, pp. 1272 – 1276. DOI 10.1109/JSSC.1985.1052468

  180. Rainal A. J.: Computing Inductive Noise of Chip Packages. AT&T Bell Lab. Techn. Journal, Vol. 63, no. 1, 1984, pp. 177 – 195.

Copyright 2010 © UNESCO - All Rights Reserved.