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ELECTROSTATIC DISCHARGE and CORONA BREAKDOWN

The cure for this is not to sit still,

Or frost with a book by the fire,

But to take a large hoe and a shovel also,

And dig till you gently perspire”

(R. Kipling)

  1. Ungru T., Wilkening W., Negra R.: New Integrated Crystal Oscillator Design with Improved Robustness Against ESD Disturbances in Operation. IEEE Trans on EMC, Vol. 60, no. 2, 2018, pp. 322 – 327. DOI 10.1109/TEMC.2017.2731969

  2. Zhou Jianchi, Gan Yingjie, Jin Hang, et al.: ESD Spark Behavior and Modeling for Geometries Having Spark Lengths Greater Than the Value Predicted by Paschen's Law. IEEE Trans on EMC, Vol. 60, no. 1, 2018, pp. 115 – 121. DOI 10.1109/TEMC.2017.2704607

  3. Yousaf Jawad, Shin Jaeyoung, Kim Kwangho, et al.: System Level ESD Coupling Analysis Using Coupling Transfer Impedance Function. IEEE Trans on EMC, Vol. 60, no. 2, 2018, pp. 310 – 321. DOI 10.1109/TEMC.2017.2707580

  4. Gan Yingjie, Talebzadeh Atieh, Xu Xiaoying, et al.: Experimental Characterization and Modeling of Surface Discharging for an Electrostatic Discharge (ESD) to an LCD Display. IEEE Trans on EMC, Vol. 60, no. 1, 2018, pp. 96 – 106. DOI 10.1109/TEMC.2017.2705619

  5. Kuznetsov Vadim: HBM, MM, and CBM ESD Ratings Correlation Hypothesis. IEEE Trans on EMC, Vol. 60, no. 1, 2018, pp. 107 – 114. DOI 10.1109/TEMC.2017.2700492

  6. Kumar B. Sampath, Shrivastava Mayank: Part II: RF, ESD, HCI, SOA, and Self Heating Concerns in LDMOS Devices Versus Quasi-Saturation. IEEE Trans on ED, Vol. 65, no. 1, 2018, pp. 199 – 206. DOI 10.1109/TED.2017.2732504

  7. Liu Yuan, Chen Rongsheng, Li Bin, et al.: Analysis of Indium-Zinc-Oxide Thin-Film Transistors Under Electrostatic Discharge Stress. IEEE Trans on ED, Vol. 65, no. 1, 2018, pp. 356 – 360. DOI 10.1109/TED.2017.2775222

  8. Jin Xiangliang, Zheng Yifei, Wang Yang, et al.: ESD robustness improving for the low-voltage triggering silicon-controlled rectifier by adding NWell at cathode. Solid-State Electronics, Vol. 139, 2018, pp. 69 – 74. DOI 10.1016/j.sse.2017.09.013

  9. Fujiwara Shuji: ESD Robustness Enhancement Study of Ultra-High-Voltage JFET with Ballast Structure. IEEE Trans on Device and Materials Reliability, Vol. 17, no. 4, 2017, pp. 616 – 623. DOI 10.1109/TDMR.2017.2751067

  10. Taka Yoshinori, Ishida Takeshi, Fujiwara Osamu: Waveform Comparison and Difference Factors in Discharge Currents for Air Discharges from Different ESD Generators. Electrical Eng. in Japan, Vol. 200, no. 1, 2017, pp. 3 – 11. DOI 10.1002/eej.22973

  11. Ichikawa Norimitsu: Experimental Consideration of the Electrostatically Induced Voltage Generated when a Charged Body Approaches a Metal Box and Moves Away from the Box. IEEE Trans on Dielectrics and Electrical Insulation, Vol. 24, no. 2, 2017, pp. 1203 – 1209. DOI 10.1109/TDEI.2017.006175

  12. Tsai Ming-Hsien, Hsu Sen-Kuei, Liu Sally, et al.: An On-Chip Electromagnetic Bandgap Structure with ESD Protection for Noise Suppression in 16-nm FinFET CMOS. IEEE Microwave & Wireless Comp. Lett., Vol. 27, no. 2, 2017, pp. 147 – 149. DOI 10.1109/LMWC.2016.2646902

  13. Lee Byung-Seok, Koo Yong-Seo: Analysis of SCR Based ESD Protection Device with Optimized Low Trigger Voltage for Low Trigger Voltage Applications. J. of Semiconductor Technology & Science, Vol. 17, no. 6, Special Issue: SI, 2017, pp. 792 – 799. DOI 10.5573/JSTS.2017.17.6.792

  14. Mishra Abhishek, Gossner Harald, Shrivastava Mayank: ESD Behavior of MWCNT Interconnects - Part I: Observations and Insights. IEEE Trans on Device and Materials Reliability, Vol. 17, no. 4, 2017, pp. 600 – 607. DOI 10.1109/TDMR.2017.2756924

  15. Mishra Abhishek, Shrivastava Mayank: ESD Behavior of MWCNT Interconnects - Part II: Unique Current Conduction Mechanism. IEEE Trans on Device and Materials Reliability, Vol. 17, no. 4, 2017, pp. 608 – 615. DOI 10.1109/TDMR.2017.2738701

  16. Dong Aihua, Salcedo Javier A., Parthasarathy Srivatsan, et al.: ESD protection structure with reduced capacitance and overshoot voltage for high speed interface applications. Microelectronics Reliability, Vol. 79, 2017, pp. 201 – 205. DOI 10.1016/j.microrel.2017.03.014

  17. Sinha Dheeraj Kumar, Chatterjee Amitabh: SPICE level implementation of physics of filamentation in ESD protection devices. Microelectronics Reliability, Vol. 79, 2017, pp. 239 – 247. DOI 10.1016/j.microrel.2017.05.022

  18. Li Ming, Fan Jiewen, Xu Xiaoyan, et al.: Investigation on Electrostatic Discharge Robustness of Gate-All-Around Silicon Nanowire Transistors Combined with Thermal Analysis. IEEE ED Lett., Vol. 38, no. 12, 2017, pp. 1653 – 1656. DOI 10.1109/LED.2017.2768484

  19. Guan Jian, Wang Yang, Hao Shanwan, et al.: A Novel High Holding Voltage Dual-Direction SCR with Embedded Structure for HV ESD Protection. IEEE ED Lett., Vol. 38, no. 12, 2017, pp. 1716 – 1719. DOI 10.1109/LED.2017.2766686

  20. Li Xiaoyun, Chen Houpeng, Lei Yu, et al.: A novel high performance 3xVDD-tolerant ESD detection circuit in advanced CMOS process. IEICE Electronics Express, Vol. 14, no. 21, 2017, Article # 20170899. DOI 10.1587/elex.14.20170899

  21. Lin Chun-Yu, Liu Rui-Hong, Ker Ming-Dou: Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process. Microelectronics Reliability, Vol. 78, 2017, pp. 258 – 266. DOI 10.1016/j.microrel.2017.09.005

  22. Liu Fan, Liu Zhiwei, Liu Jizhi, et al.: A novel vertical SCR for ESD protection in 40 V HV bipolar process. Microelectronics Reliability, Vol. 78, 2017, pp. 307 – 310. DOI 10.1016/j.microrel.2017.09.018

  23. Ye Ran, Liu Siyang, Sun Weifeng, et al.: ESD robustness concern for SOI-LIGBTs with typical latch-up immunity structures. Solid-State Electronics, Vol. 137, 2017, pp. 6 – 9. DOI 10.1016/j.sse.2017.07.010

  24. Li Xiang, Dong Shurong, Jin Hao, et al.: 28-nm CMOS process ESD protection based on diode-triggered silicon controlled rectifier. Solid-State Electronics, Vol. 137, 2017, pp. 128 – 133. DOI 10.1016/j.sse.2017.07.012

  25. Chen Jie-Ting, Lin Chun-Yu, Ker Ming-Dou: On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology. IEEE Trans on ED, Vol. 64, no. 10, 2017, pp. 3979 – 3985. DOI 10.1109/TED.2017.2734059

  26. Galy P., Bourgeat J., Guitard N., et al.: Ultracompact ESD Protection with BIMOS-Merged Dual Back-to-Back SCR in Hybrid Bulk 28-nm FD-SOI Advanced CMOS Technology. IEEE Trans on ED, Vol. 64, no. 10, 2017, pp. 3991 – 3997. DOI 10.1109/TED.2017.2741524

  27. Song Bo Bae, Lee Byung Seok, Yang Yil Suk, et al.: Analysis of a Parasitic-Diode-Triggered Electrostatic Discharge Protection Circuit for 12 V Applications. ETRI Journal, Vol. 39, no. 5, 2017, pp. 746 – 755. DOI 10.4218/etrij.17.0117.0026

  28. Ge Changfeng, Devar Ganapathi: Formation of Polyvinyl Alcohol film with graphene nanoplatelets and carbon black for electrostatic discharge protective packaging. J. of Electrostatics, Vol. 89, 2017, pp. 52 – 57. DOI 10.1016/j.elstat.2017.07.004

  29. Chuang Che-Hao, Ker Ming-Dou: System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chips. IEEE Trans on Device and Materials Reliability, Vol. 17, no. 3, 2017, pp. 570 – 576. DOI 10.1109/TDMR.2017.2737943

  30. Lu Guangyi, Wang Yuan, Wang Yize, et al.: Insights Into the Power-Off and Power-On Transient Performance of Power-Rail ESD Klamp Circuits. IEEE Trans on Device and Materials Reliability, Vol. 17, no. 3, 2017, pp. 577 – 584. DOI 10.1109/TDMR.2017.2737653

  31. Lu Guangyi, Wang Yuan, Wang Yize, et al.: Low-Leakage ESD Power Klamp Design with Adjustable Triggering Voltage for Nanoscale Applications. IEEE Trans on ED, Vol. 64, no. 9, 2017, pp. 3562 – 3568. DOI 10.1109/TED.2017.2730203

  32. Zhang Wenjie, Yang Liu, Wang Yang, et al.: Design and analysis of different trigger techniques for ESD klamp circuit in 0.5-mm 5 V/18 V CDMOS process. Solid-State Electronics, Vol. 135, 2017, pp. 8 – 13. DOI 10.1016/j.sse.2017.06.005

  33. Huang Xiaozong, Liu Zhiwei, Liu Fan, et al.: High holding voltage SCRs with segmented layout for high-robust ESD protection. Electronics Lett., Vol. 53, no. 18, 2017, pp. 1274 – 1275. DOI 10.1049/el.2017.2390

  34. Lv Zhixing, Yan Nan, Bao Bingliang: Pin-pin ESD protection for electro-explosive device under severe human body ESD. Microelectronics Reliability, Vol. 75, 2017, pp. 37 – 42. DOI 10.1016/j.microrel.2017.06.004

  35. Lin Chun-Yu, Lin Meng-Ting: Improved stacked-diode ESD protection in nanoscale CMOS technology. IEICE Electronics Express, Vol. 14, no. 13, 2017, Article # 20170570. DOI 10.1587/elex.14.20170570

  36. Lee Jian-Hsing, Iyer Natarajan Mahadeva: Analytical Model of Correlation Factor for Human-Body Model to Transmission-Line Pulse ESD Testing. IEEE ED Lett., Vol. 38, no. 7, 2017, pp. 952 – 954. DOI 10.1109/LED.2017.2708420

  37. Chen Hung-Wei, Chang Mi-Chang: Improving the ESD self-protection capability of 60 V HV p-channel LDMOS large array device in 0.25 mm BCD process. Microelectronics Reliability, Vol. 74, 2017, pp. 110 – 117. DOI 10.1016/j.microrel.2017.05.019

  38. Cho S., Lee D., Ali I., et al.: Highly reliable automotive integrated protection circuit for human body model ESD of +6 kV, over voltage, and reverse voltage. Electronics Lett., Vol. 53, no. 13, 2017, pp. 843 – 844. DOI 10.1049/el.2017.0780

  39. Choi Jin-Young: Structure Optimization of ESD Diodes for Input Protection of CMOS RF ICs. J. of Semiconductor Technology & Science, Vol. 17, no. 3, 2017, pp. 401 – 410. DOI 10.5573/JSTS.2017.17.3.401

  40. Liu JiZhi, Zeng Yaohui, Liu Zhiwei, et al.: Low-voltage triggering SCRs for ESD protection in a 0.35-mm SiGe BiCMOS process. Microelectronics Reliability, Vol. 73, 2017, pp. 122 – 128. DOI 10.1016/j.microrel.2017.04.029

  41. Lin Chun-Yu, Chen Chun-Yu: Resistor-Triggered SCR Device for ESD Protection in High-Speed I/O Interface Circuits. IEEE ED Lett., Vol. 38, no. 6, 2017, pp. 712 – 715. DOI 10.1109/LED.2017.2696980

  42. Ungru T., Wilkening W., Negra R.: Modeling of Transients on IC Supply Rails Caused by ESD During Operation. IEEE Trans on EMC, Vol. 59, no. 3, 2017, pp. 910 – 918. DOI 10.1109/TEMC.2016.2635108

  43. Wang Yize, Wang Yuan, Lu Guangyi, et al.: A novel TLP-based method to deliver IEC 61000-4-2 ESD stress. IEICE Electronics Express, Vol. 14, no. 9, 2017, Article # 20170163. DOI 10.1587/elex.14.20170163

  44. Lee Jian-Hsing, Iyer Natarajan Mahadeva, Prabhu Manjunatha: ESD Robust Fully Salicided 5-V Integrated Power MOSFET in Submicron CMOS. IEEE ED Lett., Vol. 38, no. 5, 2017, pp. 623 – 625. DOI 10.1109/LED.2017.2686638

  45. Chen Shen-Li, Huang Yu-Ting, Wu Yi-Cih: Design of High-ESD Reliability in HV Power pLDMOS Transistors by the Drain-Side Isolated SCRs. IEICE Trans on Electronics, Vol. E100C, no. 5, 2017, pp. 446 – 452. DOI 10.1587/transele.E100.C.446

  46. Liu Jizhi, Qian Lingli, Tian Rui, et al.: Self-triggered stacked silicon-controlled rectifier structure (STSSCR) for on-chip electrostatic discharge (ESD) protection. Microelectronics Reliability, Vol. 71, 2017, pp. 1 – 5. DOI 10.1016/j.microrel.2016.11.014

  47. Kim Ki-Hyuk, Talebzadeh Atieh, Pommerenke David, et al.: A study on the triboelectric charging of display glass during the roller transfer process-modeling and characterization. J. of Electrostatics, Vol. 86, 2017, pp. 24 – 33. DOI 10.1016/j.elstat.2016.12.020

  48. Wang Yuan, Lu Guangyi, Wang Yize, et al.: Power-Rail ESD Klamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness. IEICE Trans on Electronics, Vol. E100C, no. 3, 2017, pp. 344 – 347. DOI 10.1587/transele.E100.C.344

  49. Ankathi Sriharsha, Vignan Sriramula, Athukuri Srikanth, et al.: A 5-7 GHz current reuse and gm-boosted common gate low noise amplifier with LC based ESD protection in 32-nm CMOS. Analog Integrated Circuits & Signal Processing, Vol. 90, no. 3, 2017, pp. 573 – 589. DOI10.1007/s10470-016-0915-x

  50. Thomson N.A., Xiu Yang, Rosenbaum E.: Soft-Failures Induced by System-Level ESD. IEEE Trans on Device and Materials Reliability, Vol. 17, no. 1, 2017, pp. 90 – 98. DOI 10.1109/TDMR.2017.2667712

  51. Keel Min-Sun, Rosenbaum E.: ESD Self-Protection of High-Speed Transceivers Using Adaptive Active Bias Conditioning. IEEE Trans on Device and Materials Reliability, Vol. 17, no. 1, 2017, pp. 113 – 120. DOI 10.1109/TDMR.2016.2628839

  52. Ker Ming-Dou, Chiu Po-Yen, Shieh Wuu-Trong, et al.: ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test. IEEE Trans on ED, Vol. 64, no. 2, 2017, pp. 642 – 645. DOI 10.1109/TED.2016.2642042

  53. Athanasiou S., Legrand C.-A., Cristoloveanu S., et al.: Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28-nm FD-SOI technology. Solid-State Electronics, Vol. 128, Special Issue: SI, 2017, pp. 172 – 179. DOI 10.1016/j.sse.2016.10.026

  54. Son Minoh, Park Changkun: Cell-Based ESD Diodes with a Zigzag-Shaped Layout to Enhance the ESD Survival Level. J. of Circuits, Systems & Computers, Vol. 26, no. 2, 2017, Article # 1750023. DOI 10.1142/S0218126617500232

  55. Li Xiaoyun, Chen Houpeng, Wang Qian, et al.: Enhanced 3xVDD-tolerant ESD klamp circuit with stacked configuration. IEICE Electronics Express, Vol. 14, no. 2, 2017, Article # 20160901. DOI 10.1587/elex.14.20160901

  56. Alad Rizwan H., Shah Haely, Chakrabarty Soumyabrata, et al.: Effect of Solar Illumination on ESD for Structure Used in Spacecraft. Progress in Electromagnetics Research M, Vol. 55, 2017, pp. 25 – 36. DOI 10.2528/PIERM16120107

  57. Kwak Jae Chang: Design of fabrication of ESD protection circuit with high holding voltage for power IC. Int. J. of Electronics, Vol. 104, no. 12, 2017, pp. 2090 – 2098. DOI 10.1080/00207217.2017.1335795

  58. Kocer Fatih: An RC-triggered ESD klamp for high-voltage BCD CMOS processes. Turkish J. of Electrical Eng. and Computer Sciences, Vol. 25, no. 4, 2017, pp. 3435 – 3442. DOI 10.3906/elk-1610-49

  59. Park Junsik, Lee Jongsung, Seol Byongsu, et al.: Fast and Accurate Calculation of System-Level ESD Noise Coupling to a Signal Trace by PEEC Model Decomposition. IEEE Trans on MTT, Vol. 65, no. 1, 2017, pp. 50 – 61. DOI 10.1109/TMTT.2016.2615620

  60. Kranthi Nagothu Karmel, Shrivastava Mayank: ESD Behavior of Tunnel FET Devices. IEEE Trans on ED, Vol. 64, no. 1, 2017, pp. 28 – 36. DOI 10.1109/TED.2016.2630079

  61. Nakaya Ryo, Ando Hidenawo, Anzai Daisuke, et al.: Statistical Measurement of Electromagnetic Noise Characteristics of ESD in Wireless Frequency Bands and Influence Evaluation on Communication Performance. IEICE Trans on Communications, Vol. E99B, no. 11, 2016, pp. 2399 – 2405. DOI 10.1587/transcom.2015EBP3527

  62. Lu Guangyi, Wang Yuan, Zhang Lizhong, et al.: Design of a novel static-triggered power-rail ESD klamp circuit in a 65-nm CMOS process. Science China-Information Sciences, Vol. 59, no. 12, 2016, Article # 122401. DOI 10.1007/s11432-015-5455-y

  63. Mitra Souvick, Gebreselasie Ephrem, Li You, et al.: 3-D Integration and ESD Protection: Design and Analysis. IEEE Trans on Device and Materials Reliability, Vol. 16, no. 4, 2016, pp. 497 – 503. DOI 10.1109/TDMR.2016.2627522

  64. Notermans G., Ritter H.-M., Utzig J., et al.: Design of an On-Board ESD Protection for USB3 Applications. IEEE Trans on Device and Materials Reliability, Vol. 16, no. 4, 2016, pp. 504 – 512. DOI 10.1109/TDMR.2016.2622400

  65. Altolaguirre Federico A., Ker Ming-Dou: Low-Leakage Bidirectional SCR with Symmetrical Trigger Circuit for ESD Protection in 40-nm CMOS Process. IEEE Trans on Device and Materials Reliability, Vol. 16, no. 4, 2016, pp. 549 – 555. DOI 10.1109/TDMR.2016.2600276

  66. Lin Chun-Yu, Fu Wei-Hao: Diode String with Reduced Klamping Voltage for Efficient On-Chip ESD Protection. IEEE Trans on Device and Materials Reliability, Vol. 16, no. 4, 2016, pp. 688 – 690. DOI 10.1109/TDMR.2016.2616719

  67. Lu Guangyi, Wang Yuan, Zhang Xing: Transient and Static Hybrid-Triggered Active Klamp Design for Power-Rail ESD Protection. IEEE Trans on ED, Vol. 63, no. 12, 2016, pp. 4654 – 4660. DOI 10.1109/TED.2016.2618344

  68. Zeng Jie, Dong Shurong, Wong Hei, et al.: Layout optimization of GGISCR structure for on-chip system level ESD protection applications. Solid-State Electronics, Vol. 126, 2016, pp. 152 – 157. DOI 10.1016/j.sse.2016.08.004

  69. Li Xiang, Dong Shurong, Yu Zhihui, et al.: Transient Voltage Suppressor Based on Diode-Triggered Low-Voltage Silicon Controlled Rectifier. Facta Universitatis - Series Electronics and Energetics, Vol. 29, no. 4, 2016, pp. 647 – 651. DOI 10.2298/FUEE1604647L

  70. Liao Changjun, Liu Jizhi, Liu Zhiwei: New fast turn-on speed SCR device for electrostatic discharge protection. Microelectronics Reliability, Vol. 66, 2016, pp. 38 – 45. DOI 10.1016/j.microrel.2016.09.006

  71. Liang Wei, Dong Aihua, Li Hang, et al.: Characteristics of ESD protection devices operated under elevated temperatures. Microelectronics Reliability, Vol. 66, 2016, pp. 46 – 51. DOI 10.1016/j.microrel.2016.10.008

  72. Lin Chun-Yu, Wu Yi-Han, Ker Ming-Dou: Low-Leakage and Low-Trigger-Voltage SCR Device for ESD Protection in 28-nm High-k Metal Gate CMOS Process. IEEE ED Lett., Vol. 37, no. 11, 2016, pp. 1387 – 1390. DOI 10.1109/LED.2016.2608721

  73. Miao Meng, Zhou Yuanzhong, Salcedo Javier A., et al.: A New Method to Estimate Failure Temperatures of Semiconductor Devices Under Electrostatic Discharge Stresses. IEEE ED Lett., Vol. 37, no. 11, 2016, pp. 1477 – 1480. DOI 10.1109/LED.2016.2608328

  74. Chen Shen-Li, Lee Min-Hua: Reliability Analysis of P+ Pickup on Anti-ESD Performance in Four CMOS Low-Voltage Technology Nodes. IETE Journal of Research, Vol. 62, no. 6, 2016, pp. 752 – 761. DOI 10.1080/03772063.2016.1164634

  75. Ding Yi, Hu Jianguo, Duan Zhikui, et al.: Built-in ESD Protection for RFID Tag ICs. Chinese Journal of Electronics, Vol. 25, no. 6, 2016, pp. 1058 – 1062. DOI 10.1049/cje.2016.06.013

  76. Habib Nazmul, Muhammad Mujahid, Bickford J.P., et al.: Deep Trench Capacitor in Three Dimensional Through Silicon via Keepout Area for Electrostatic Discharge Protection. IEEE Trans on Semiconductor Manufacturing, Vol. 29, no. 4, 2016, pp. 292 – 298. DOI 10.1109/TSM.2016.2587809

  77. Lin Chun-Yu, Chiu Yu-Kai, Yueh Shuan-Yu: Design of local ESD klamp for cross-power-domain interface circuits. IEICE Electronics Express, Vol. 13, no. 20, 2016, Article # 20160806. DOI 10.1587/elex.13.20160806

  78. Huang Xiaozong, Liou Juin J., Liu Zhiwei, et al.: A New High Holding Voltage Dual-Direction SCR with Optimized Segmented Topology. IEEE ED Lett., Vol. 37, no. 10, 2016, pp. 1311 – 1313. DOI 10.1109/LED.2016.2598063

  79. Lu Fei, Ma Rui, Dong Zongyu, et al.: A Systematic Study of ESD Protection Co-Design with High-Speed and High-Frequency ICs in 28-nm CMOS. IEEE Trans on CAS I : Regular Papers, Vol. 63, no. 10, 2016, pp. 1746 – 1757. DOI 10.1109/TCSI.2016.2581839

  80. Gan Yingjie, Xu Xiaoying, Maghlakelidze Giorgi, et al.: System-Level Modeling Methodology of ESD Cable Discharge to Ethernet Transceiver Through Magnetics. IEEE Trans on EMC, Vol. 58, no. 5, 2016, pp. 1407 – 1416. DOI 10.1109/TEMC.2016.2581884

  81. Lin Chun-Yu, Chiu Yan-Lian: Design of embedded SCR device to improve ESD robustness of stacked-device output driver in low-voltage CMOS technology. Solid-State Electronics, Vol. 124, 2016, pp. 28 – 34. DOI 10.1016/j.sse.2016.07.029

  82. Chen S.-L., Chen K.-J., Chen H.-W.: ESD protection design and enhancement in the power 60-V n-channel LDMOS by embedded-SCR anode islands. Electronics Lett., Vol. 52, no. 19, 2016, pp. 1639 – 1640. DOI 10.1049/el.2016.2232

  83. Song Bo Bae, Koo Yong Seo: Low Ron and high robustness ESD protection design for low-voltage power klamp application. Electronics Lett., Vol. 52, no. 18, 2016, pp. 1554 – 1555. DOI 10.1049/el.2016.2391

  84. Escudie F., Caignet F., Nolhier N., et al.: Impact of non-linear capacitances on transient waveforms during system level ESD stress. Microelectronics Reliability, Vol. 64, Special Issue: SI, 2016, pp. 88 – 92. DOI 10.1016/j.microrel.2016.07.046

  85. Viale B., Fer M., Courau L., et al.: On the need for a new ESD verification methodology to improve the reliability of ICs in advanced 28-nm UTBB FD-SOI technology. Microelectronics Reliability, Vol. 64, Special Issue: SI, 2016, pp. 101 – 108. DOI 10.1016/j.microrel.2016.07.076

  86. Irace A., Maresca L., Mirone P., et al.: 200 V Fast Recovery Epitaxial Diode with Superior ESD Capability. Microelectronics Reliability, Vol. 64, Special Issue: SI, 2016, pp. 440 – 446. DOI 10.1016/j.microrel.2016.07.022

  87. Vanzi M., Mura G., Marcello G., et al.: ESD tests on 850-nm GaAs-based VCSELs. Microelectronics Reliability, Vol. 64, Special Issue: SI, 2016, pp. 617 – 622. DOI 10.1016/j.microrel.2016.07.023

  88. Chen Shih-Hung, Hellings Geert, Thijs Steven: Process Options Impact on ESD Diode Performance in Bulk FinFET Technology. IEEE Trans on ED, Vol. 63, no. 9, 2016, pp. 3424 – 3431. DOI 10.1109/TED.2016.2597000

  89. Rose Matthias, Bergveld Henk Jan: Integration Trends in Monolithic Power ICs: Application and Technology Challenges. IEEE Journal of Solid State Circ., Vol. 51, no. 9, 2016, pp. 1965 – 1974. DOI 10.1109/JSSC.2016.2566612

  90. Wu Cheng-Hsu, Lee Jian-Hsing, Lien Chen-Hsin: A New Low-Voltage Triggering SCR for the Protection of a Double RESURF HV-LDMOS. IEEE ED Lett., Vol. 37, no. 9, 2016, pp. 1201 – 1203. DOI 10.1109/LED.2016.2594441

  91. Meng Kuo-hsuan, Chen Zaichen, Rosenbaum E.: Compact distributed multi-finger MOSFET model for circuit-level ESD simulation. Microelectronics Reliability, Vol. 63, 2016, pp. 11 – 21. DOI 10.1016/j.microrel.2015.12.010

  92. Talebzadeh Atieh, Moradian Mahdi, Han Yunan, et al.: Effect of Human Activities and Environmental Conditions on Electrostatic Charging. IEEE Trans on EMC, Vol. 58, no. 4, Special Issue: SI, Part: 2, 2016, pp. 1266 – 1273. DOI 10.1109/TEMC.2016.2575842

  93. Lambrecht N., Gazda C., Pues H., et al.: Efficient Circuit Modeling Technique for the Analysis and Optimization of ISO 10605 Field Coupled Electrostatic Discharge (ESD) Robustness of Nonlinear Devices. IEEE Trans on EMC, Vol. 58, no. 4, Part: 1, 2016, pp. 971 – 980. DOI 10.1109/TEMC.2016.2553173

  94. Huang Chih-Yao, Chiu Fu-Chien, Ou Chien-Min, et al.: ESD and Latchup Optimization of an Embedded-Floating-pMOS SCR-Incorporated BJT. IEEE Trans on ED, Vol. 63, no. 8, 2016, pp. 3036 – 3043. DOI 10.1109/TED.2016.2582848

  95. Altolaguirre Federico A., Ker Ming-Dou: Quad-SCR Device for Cross-Domain ESD Protection. IEEE Trans on ED, Vol. 63, no. 8, 2016, pp. 3177 – 3184. DOI 10.1109/TED.2016.2579170

  96. Huang Yi-Jie, Ker Ming-Dou: Investigation of Human-Body-Model and Machine-Model ESD Robustness on Stacked Low-Voltage Field-Oxide Devices for High-Voltage Applications. IEEE Trans on ED, Vol. 63, no. 8, 2016, pp. 3193 – 3198. DOI 10.1109/TED.2016.2583380

  97. Chen Qi, Ma Rui, Zhang Wei, et al.: Systematic Characterization of Graphene ESD Interconnects for On-Chip ESD Protection. IEEE Trans on ED, Vol. 63, no. 8, 2016, pp. 3205 – 3212. DOI 10.1109/TED.2016.2582140

  98. Zhang Tao, Gui Ping, Chakraborty Sudipto, et al.: 10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS. IEEE Trans on VLSI Systems, Vol. 24, no. 7, 2016, pp. 2502 – 2510. DOI 10.1109/TVLSI.2015.2507438

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